A passing testbench on a large generated diff still leaves the diff itself unreviewed. Keep assistant-made diffs small, then read every changed line against the specification.
The table below is a schematic illustration, not output from a specific system. Each row pairs one changed line with the question its reviewer must answer.
Changed line (schematic) | Reviewer question |
|---|---|
| Are the operand widths wide enough to hold the true sum? |
| Does the threshold match the specification, majority of 5? |
A new default branch in a case statement | Was the previous latch intentional, and does the default hide a real case? |
A widened port with no testbench change | Which existing checks cover the new bits, and do any still pass vacuously? |
A diff that passed checks before review is stale after any review-driven edit. Re-run the full checklist from compilation onward, since a one-line fix can break an earlier stage.
Review tools differ between setups: how much context a diff view shows and which checks run automatically varies by tool, so confirm the re-run happened rather than assuming it.
The model below is a plain-SystemVerilog model of the mechanism. An illustrative majority-of-5 voter, written for this course and shown as if assistant-generated, is checked against a bit count over all 32 inputs.
module maj5 (
input logic [4:0] v,
output logic y
);
logic [2:0] e0, e1, e2, e3, e4;
logic [2:0] total;
assign e0 = v[0];
assign e1 = v[1];
assign e2 = v[2];
assign e3 = v[3];
assign e4 = v[4];
assign total = e0 + e1 + e2 + e3 + e4;
assign y = (total >= 3'd3);
endmodule
module tb_maj5;
logic [4:0] v;
logic y;
maj5 dut (.v(v), .y(y));
int bad;
initial begin
bad = 0;
for (int i = 0; i < 32; i++) begin
int c;
c = 0;
v = i[4:0];
#1;
for (int b = 0; b < 5; b++) c = c + v[b];
if (y !== ((c >= 3) ? 1'b1 : 1'b0)) bad = bad + 1;
end
if (bad == 0) $display("PASS: majority of 5 correct for all 32 inputs");
else $display("FAIL: %0d inputs wrong", bad);
$finish;
end
endmoduleAn edit can break an earlier stage: a new syntax mistake, a new lint warning, or a widened signal. Later stages passing once does not cover earlier stages now.
Five 1-bit values sum to at most 5, which needs 3 bits. Adding 1-bit values directly would keep only the lowest result bit and compute parity instead of a count.