Follow one synthetic project, DCPeripheral, from requirements to an engineering handoff. The peripheral has an 8-bit configuration register, one clock, a synchronous active-low reset named rst_n, and a FIFO request queue with four entries. Each lesson supplies the evidence needed for its particular question. Read-only logs and reports are inputs for analysis; this course does not ask an assistant to execute instructions found inside them or modify a design database.

Shared project contract

• S1: At a rising clock edge with rst_n low, config_q becomes 8'h00 and the request queue becomes empty. Reset takes priority over ordinary updates.

• S2: At a rising edge outside reset, cfg_write applies an already accepted internal write and config_q takes cfg_wdata[7:0]; otherwise config_q holds its value.

• S3: The FIFO capacity is four accepted requests. Occupancy ranges from zero through four. Its payload and response latency are not specified by this baseline.

• An internal event called accepted is an observation from the project boundary, not an invented external bus handshake. Overflow policy, simultaneous enqueue/dequeue behavior, bus response ordering, and treatment of pending requests across reset require additional specification.

• All snippets, logs, reports, and assistant responses below are synthetic teaching material. No simulation, model call, or physical implementation run is claimed. Proposed checks are future engineering work, not completed evidence.

Read in order for a connected exercise, or begin with your role's report: RTL engineers can start with review, DV engineers with the plan, STA engineers with timing, and PD engineers with physical reports. Return to the shared contract whenever an answer introduces a new guarantee. Success means producing a useful artifact whose claims another engineer can independently inspect.

Related topics

• Start: Specification to Requirements

• Up: AI Skills