A mismatch log says expected 0xA5, observed 0x00. An assistant may immediately blame the DUT register. A scoreboard compares observed behavior with a model of expected behavior, so either side of that comparison can be wrong. Begin with acceptance events, reset edges, and the precise observation being compared. DCPeripheral has no baseline read-response timing guarantee; this lesson compares an internal register observation rather than inventing one.
SYNTHETIC evidence bundle SB-A, hand-authored:
Boundary event log (values sampled before each rising edge):
edge 10: rst_n=1, cfg_write=1, cfg_wdata=A5
edge 11: rst_n=0, cfg_write=0
edge 12: rst_n=1, cfg_write=0
Register observer: after edge 12 sequential updates, config_q=00
Scoreboard comparison at that same observation: expected=A5, observed=00
Scoreboard update excerpt:
if cfg_write and rst_n: expected_config = cfg_wdata
# No reset branch is present in the supplied excerpt.The boundary log defines cfg_write as an accepted internal write, so edge 10 changes the expected register to A5. Edge 11 then satisfies S1 and must clear it to zero. With no new write at edge 12, zero is still expected. This gives a concrete bookkeeping explanation for the mismatch: the supplied scoreboard fragment preserves A5 through reset. It is a stronger local explanation than a story about dropped requests because it follows every supplied state-changing event.
PROMPT:
Analyze SB-A as read-only evidence. Reconstruct expected_config by edge.
Return facts, hypotheses, and the smallest additional evidence needed.
Do not change expected values just to match the DUT.
Do not infer external response ordering or latency.Edge | Contract-based state after edge | Why |
|---|---|---|
10 | A5 | Accepted write outside reset |
11 | 00 | Synchronous reset has priority |
12 | 00 | No accepted write after reset |
A useful synthetic response says the missing reset branch explains the stale expected register if this excerpt is the whole relevant update path. It also asks whether the monitor captured reset correctly and whether a second process updates the model. The observer's stated post-update sampling removes one ambiguity for this example, but a real log must establish that convention. Comparing a pre-update expected value with a post-update observation can produce a different mismatch even when both components implement their own intended rules.
A separate synthetic FIFO boundary check makes the sampling distinction concrete. Outside reset, assume pre-edge occupancy is three and one enqueue-only event is legitimately accepted. The expected post-update occupancy is four. Compare that expectation with a post-update observation of the same edge; comparing it with the old pre-edge value of three would manufacture a mismatch. This internal check does not specify external response timing.
Propose the smallest register-model change and two future scenarios to distinguish bookkeeping repair from error masking. Keep the request scoreboard separate. In the first scenario repeat SB-A. In the second, write 0x3C outside reset and deliberately describe a DUT observation of 0x00. State whether each comparison should pass or fail and why. Name the artifact required before deciding how pending transaction expectations survive reset.
Update the register model with reset priority: if reset is sampled low set expected_config=0; else if cfg_write set it to cfg_wdata. Repeating SB-A should compare 00 with 00. A later accepted 3C write with an observed 00 must still fail. Obtain the interface/reset cancellation contract before clearing pending response expectations; no four-response ignore window is justified.
Keep the original mismatch, event bundle, and proposed correction linked in the issue. This analysis does not show a rerun or prove the DUT correct outside the supplied trace. If logs omit accepted events or reset observations, label the timeline incomplete. The Accellera UVM 1.2 User's Guide, October 8, 2015, describes monitor and scoreboard roles; the mechanics here do not require adopting UVM or adding dependencies.