An RTL engineer asks an assistant whether a small DCPeripheral fragment matches revision A. Start with the contract: reset is synchronous and active low, config_q is eight bits, and queue occupancy must represent zero through four. The fragment below intentionally contains two review targets. It omits ports, queue storage, dequeue logic, and acceptance generation. A supported finding must name its local evidence and explain the consequence without pretending those missing parts were reviewed.
// bad-example: synthetic partial RTL for review; not a complete module.
logic [7:0] config_q;
logic [1:0] occupancy;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
config_q <= 8'h00;
occupancy <= 2'd0;
end else begin
if (cfg_write) config_q <= cfg_wdata;
if (enqueue_only) occupancy <= occupancy + 2'd1;
end
endHere cfg_wdata is declared eight bits in the supplied interface, and enqueue_only means an already accepted enqueue with no dequeue that edge. It is only a local event label. Nothing in this fragment establishes when the external interface accepts a request. Asking the model to diagnose the whole protocol from this name would give it an opportunity to invent missing rules.
PROMPT:
Compare this fragment with DCPeripheral revision A.
For each finding return: requirement, exact code evidence, consequence,
smallest correction proposal, and a future check.
Keep missing context separate from defects. Analyze only the supplied RTL.Synthetic finding | Evidence and consequence | Correction proposal |
|---|---|---|
Reset behavior conflicts with S1 | negedge rst_n schedules reset activity between rising clock edges | Use a rising-clock-only event control for synchronous reset |
Occupancy cannot encode full capacity | logic [1:0] represents only 0..3; incrementing 3 loses the carry | Use at least three bits for occupancy 0..4 |
Full/empty policy cannot be assessed | Acceptance generation and dequeue handling are absent | Request those definitions; do not invent a guard |
The width issue is specific to occupancy, not every FIFO signal. A two-bit index can address four entries, while a count needs a fifth distinct state for full. This distinction helps you reject broad advice such as making every pointer three bits. The reset correction also changes an observable behavior: lowering rst_n between rising edges must not itself clear the synchronous register. The next rising edge performs the clear. Active-low polarity and asynchronous sensitivity are independent properties.
Draft only the two declaration/event-control corrections, then describe one trace that exposes each original problem. Start the register at 0xA5 and lower reset halfway between clock edges. For the count example, assume an enqueue-only event is legitimately accepted when occupancy is three. Explain what you would inspect after the edge and which extra guard cannot yet be written from the evidence.
Use logic [2:0] occupancy and always_ff @(posedge clk). In the synchronous proposal, config_q stays 0xA5 until a rising edge samples reset low, then becomes zero after the update. A legal increment from three needs to produce four; the original two-bit assignment wraps to zero. Full acceptance and simultaneous enqueue/dequeue guards require additional context.
These are correction proposals, not a validated patch. Widening a declaration also requires reviewing constants, comparisons, arithmetic, connections, and any dependent assertions. A complete review must include accepted-event definitions, full and empty transitions, and reset interaction with consumers. No lint, elaboration, or simulation result is supplied here. IEEE 1800-2023 SystemVerilog, available through the Accellera IEEE GET announcement, is the language reference for event controls, vector widths, and sequential constructs; tool support must be checked in the actual environment.