Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • RTL Foundations57
  • Combinational Design58
    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
      • Mux Theory and Design Patterns
      • A Parameterized Mux
      • Binary Decoder and One-Hot Enables
      • Priority Encoder
      • Key takeaways
      • Common pitfalls
      • Worked Examples and Waveforms
      • Corner Cases and Stress Tests
      • Integration and Sign-off Notes
    • Arithmetic Blocks
    • Comparators and Shifters
    • Tri-State and Shared Buses
    • Latch Inference
    • Arithmetic Datapaths
  • Sequential Design61
  • FSM & Control66
  • Timing & Clocking64
  • Reset & CDC58
  • Memory & Buses94
  • Advanced RTL60
  • Senior & Interview117
Loading lesson

‹Combinational Design
  1. Topics
  2. RTL Design
  3. Combinational Design
  4. Muxes, Decoders and Encoders

Part 2 · Combinational · Intermediate

Muxes, Decoders and Encoders

Muxes pick one input, decoders wake one line, and encoders report the active request.

  • 9topics
  • 9lessons

Topics in this section

  1. 1Mux Theory and Design Patterns1 lesson
  2. 2A Parameterized Mux1 lesson
  3. 3Binary Decoder and One-Hot Enables1 lesson
  4. 4Priority Encoder1 lesson
  5. 5Key takeaways1 lesson
  6. 6Common pitfalls1 lesson
  7. 7Worked Examples and Waveforms1 lesson
  8. 8Corner Cases and Stress Tests1 lesson
  9. 9Integration and Sign-off Notes1 lesson
On this page

    Datapaths steer with three blocks. A mux picks one input, a decoder wakes one line, and an encoder reports which line is active.

    Block

    Function

    Inputs → outputs

    Typical use

    Multiplexer (mux)

    Chooses one of N inputs

    N data + select → 1

    Register-file read, ALU result select

    Decoder

    Converts a binary code to one active line

    log₂N → N (one-hot)

    Address decode, write enables

    Encoder

    Converts one-hot lines back to a binary code

    N → log₂N

    Interrupt number, request index

    Priority encoder

    An encoder that tolerates several active lines

    N → log₂N + valid

    Arbitration, find-first-set

    Relationship between mux, decoder, encoder and priority encoder.
    A decoder and an encoder are inverses for one-hot data; the priority encoder generalizes the encoder to many active inputs.

    Lessons in this topic

    4 lessons, about 18 min

    1. 1Mux Theory and Design PatternsYou can build an N:1 mux as a tree of 2:1 muxes, choose between case, array and AND-OR forms, and explain unique, priority, casez and casex.6 min
    2. 2A Parameterized MuxYou can write a parameterized mux on a packed vector, size its select with $clog2, and choose what invalid selects do.4 min
    3. 3Binary Decoder and One-Hot EnablesYou can write a decoder with enable for a register map, state the one-hot invariant, and check it with $onehot0 and !$isunknown.4 min
    4. 4Priority EncoderYou can write a priority encoder with a valid output, say which bit wins in each loop direction, and speed it up for wide requests.4 min
    Check yourself A 3-to-8 decoder is followed by an 8-to-3 encoder. What is the output, and what happens if the decoder is disabled?

    With the decoder enabled, the encoder returns the original 3-bit code. With the decoder disabled, all lines are 0 and a plain encoder has no valid answer: a priority encoder with a valid output flags that case explicitly.

    Check yourself One result bus carries five data words, and a 3-bit select picks among them. Which block does the job, and what must selects 5 to 7 do?

    A mux picks the word. Selects 5 to 7 are out of range, so the mux must define them: later lessons return 0 or assert they never happen.

    Interview

    “Design an 8:1 mux from 2:1 muxes” and “write a priority encoder” are classic whiteboard tasks. The point is the clean, parameterized, latch-free coding of each.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Mux Theory and Design Patterns

    • An N:1 mux is a tree of 2:1 muxes with depth ceil(log2 N).

    • Plain case with a default is the safe choice. Avoid casex, because X and Z in the selector become wildcards.

    • AND-OR form is for selects that are already one-hot; with no select active it gives 0.

    Rule of thumb: give every case a default, or assign the output before it.

    A Parameterized Mux

    • Pack the inputs into one NW vector and pick input i with the part-select [iW +: W].

    • Guard the select width for N = 1, because $clog2(1) is 0.

    • Guard with sel < N. For a power-of-two N the tool removes the guard for free.

    Rule of thumb: decide what an out-of-range select does, and write it down.

    Binary Decoder and One-Hot Enables

    • A k-bit decoder gives 2^k outputs with one high; with enable low, all are low.

    • $onehot0(we) is true for zero or one bit set, but it does not reject X, so also check !$isunknown(we).

    • Wide address decodes are built in stages, because each select bit doubles the outputs.

    Rule of thumb: use one decoder, not a chain of address comparisons that must be edited when the map changes.

    Priority Encoder

    • Always output valid with the index, because index 0 is ambiguous without it.

    • Scanning from the high index down lets the lowest set bit overwrite last and win. Reverse the loop for highest-first.

    • A literal loop has depth proportional to N; for 32 or 64 inputs use a tree.

    Rule of thumb: carry the valid flag with the index.

    Practise it

    • Mini project: a 32-bit leading-zero counter and normaliser

    • Practice question: Write a 2:1 multiplexer in SystemVerilog

    • Code lab: Build a 4-bit 4:1 mux

    • Practice question: A parameterized-width multiplexer written to be testable

    • Practice question: A 3-to-8 decoder with enable: one-hot guarantees and X-propagation

    • Code lab: Build a 2:4 decoder

    • Interview: run a mock interview on this topic

    PreviousNext: Mux Theory and Design Patterns

    Up next

    Up nextMux Theory and Design Patterns

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Combinational Timing Overview
    • Arithmetic Blocks
    • Comparators and Shifters