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Course contents

  • RTL Foundations36
  • Combinational Design25
    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
      • Mux Theory and Design Patterns
      • A Parameterized Mux
      • Binary Decoder and One-Hot Enables
      • Priority Encoder
    • Arithmetic Blocks
    • Comparators and Shifters
    • Tri-State and Shared Buses
    • Latch Inference
    • Arithmetic Datapaths
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹Muxes, Decoders and Encoders
  1. Topics
  2. RTL Design
  3. Combinational Design
  4. Muxes, Decoders and Encoders
  5. Priority Encoder

Part 2 · Combinational · Intermediate

Priority Encoder

A priority encoder names the first active request and flags idle with valid.

On this page

    Why this matters

    With an idle bus, a priority encoder that returns index 0 looks like a request for input 0. The valid flag is what separates the two, and a literal loop is as deep as the number of inputs.

    After this lesson you can: write a priority encoder with a valid output, say which bit wins in each loop direction, and speed it up for wide requests.

    The problem

    Several requesters may be active at once, and you must pick one. A priority encoder outputs the index of the highest-priority active input.

    A valid flag says whether any input was active at all. Without it, index 0 cannot tell request 0 from nothing requested.

    req[3:0]

    valid

    idx (lowest set bit wins)

    0000

    0

    don't care (0)

    0001

    1

    0

    0010

    1

    1

    0110

    1

    1

    1000

    1

    3

    1111

    1

    0

    Naming the lowest set bit

    Watch the bottom two rows, idx and valid. The lowest set bit always wins.

    The diagram shows hex values without the 0x.

    • Slot 1: req is 0x00, so valid is 0 and idx is 0 (idle).

    • Slot 2: req is 0x04, so bit 2 wins and idx is 2.

    • Slot 3: req is 0x05, so bits 0 and 2 ask and bit 0 wins.

    • Slot 4: req is 0xA0, so bits 5 and 7 ask and bit 5 wins.

    • Slot 5: req is 0x80, so only bit 7 asks and idx is 7.

    The loop that finds it

    The loop is not a software loop. It unrolls into a chain of conditional overrides in hardware.

    Scanning from the high index down means later (lower-index) matches overwrite earlier ones, so the lowest set bit wins. Reverse the loop direction to give the highest bit priority.

    Iteration for req = 8'hA0

    req[i]

    idx after iteration

    valid

    Defaults, before the loop

    --

    0

    0

    i = 7

    1

    7 (first write)

    1

    i = 6

    0

    7 (retained)

    1

    i = 5

    1

    5 (overwrites 7)

    1

    i = 4, 3, 2, 1, 0

    All 0

    5 (retained)

    1

    These are blocking writes within one combinational evaluation, not five clock cycles. Predict the result if bit 0 is also set: the last matching iteration overwrites 5 with 0. The testbench below keeps an independent upward scan that stops accepting matches after the first set bit.

    Depth and alternatives

    • This form has depth proportional to N when built literally. For small N it is fine; synthesis often restructures it.

    • For wide requests (32 or 64), use a tree: encode each half, then combine with the half's valid flags. The depth becomes log₂ N.

    • A related trick isolates the lowest set bit with req & -req (the two's complement identity), useful for arbiters.

    Common mistakes

    Common pitfall

    If you drop the valid output and treat idx == 0 as “request 0”, an idle bus looks like a request for index 0. Always carry the valid flag with the index.

    Interview

    Priority encoder variants are a favourite: lowest-first vs highest-first, with or without valid, parameterized N, and “now make it fast for N = 64”.

    Check yourself Nobody requests: req reads 0000. What do valid and idx read?

    valid reads 0 and idx reads 0 as a don't-care. The flag carries the meaning, not the index.

    Check yourself Which request does a priority encoder select for req = 8'b0101_0100 when the lowest index has priority, and what is the index if the highest index has priority?

    Lowest-first selects bit 2 (the least significant set bit). Highest-first selects bit 6.

    Testbench

    The parameterized encoder plus a testbench that checks all 256 request patterns.

    prio_enc.sv
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    module prio_enc #(parameter int N = 8) (   // N must be at least 1
      input  logic [N-1:0]          req,
      output logic [(N > 1 ? $clog2(N) : 1)-1:0] idx,
      output logic                  valid
    );
      // N = 1 guard ($clog2(1) is 0, so [$clog2(N)-1:0] would be [-1:0]).
      localparam int SW = (N > 1) ? $clog2(N) : 1;
      always_comb begin
        idx   = '0;
        valid = 1'b0;
        for (int i = N-1; i >= 0; i--) begin       // scan from the HIGH end so the LOWEST index wins last
          if (req[i]) begin
            idx   = i[SW-1:0];
            valid = 1'b1;
          end
        end
      end
    endmodule
    

    Remember

    • Always output valid with the index, because index 0 is ambiguous without it.

    • Scanning from the high index down lets the lowest set bit overwrite last and win. Reverse the loop for highest-first.

    • A literal loop has depth proportional to N; for 32 or 64 inputs use a tree.

    Rule of thumb: carry the valid flag with the index.

    Keep going

    • Practice: A 4:2 priority encoder in SystemVerilog

    • Practice: A priority encoder with parameterized width and a valid output

    • Code lab: Build a 4:2 priority encoder

    • Interview: run a mock interview on this topic

    Related topics

    • Critical-path mindset

    • Round-robin arbiter from a priority encoder

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    See also

    • Mux Theory and Design Patterns
    • A Parameterized Mux
    clkreq045a080idx02057valid
    A priority encoder naming the lowest set bit