On-chip memory and standard buses connect datapaths to software and peripherals. This section covers inference rules, flow control, AXI family basics, SoC bus integration, and robust single-clock buffering.
Topic | Lessons | After it you can… | Study time |
|---|---|---|---|
6 | Write portable single-port, dual-port, and ROM templates. | 50 min | |
3 | Build a multi-port register file with correct bypass. | 25 min | |
4 | Apply flow-control rules and absorb backpressure with a skid buffer. | 25 min | |
5 | Write a register-mapped slave with correct strobes and responses. | 30 min | |
3 | Move packet data with TLAST and TKEEP framing. | 25 min | |
6 | Decode an address map and handle muxing, errors, and arbitration. | 40 min | |
7 | Build and verify an arbitrary-depth FIFO with explicit boundary and latency contracts. | 2–3 h | |
9 | Implement and generate CSR semantics, atomic updates, interrupts, and bus adapters. | 3–4 h | |
7 | Add parity/SECDED, reporting, scrubbing, injection, and repair hooks. | 3 h | |
5 | Build a reusable shell around protocol engines, FIFOs, interrupts, and DMA. | 2 h | |
2 | Plan bursts, IDs, ordering, and outstanding state, then continue in Protocols. | 45 min |
Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.
Only when valid and ready are high in the same cycle. Either side may wait, and the payload must stay stable while the source waits. The Valid/Ready Handshakes topic builds the rules, the skid buffer, and the AXI interpretation.
Use these four questions to decide whether you are ready to move on: explain, predict, implement and debug. If one is shaky, each answer names the lesson to revisit. New readers can skip this until they finish the section.
A source must not wait for ready before asserting valid, and once valid is high it must hold valid and the data stable until the handshake (valid && ready at a clock edge). The receiver may wait for valid before asserting ready. Revisit Rules that keep flow control safe.
Read-first returns the old contents at that address; write-first returns the data being written. Code it the way the target memory behaves, or the RTL and the inferred RAM disagree. Revisit Read-first vs write-first behavior.
count. How does count change when push and pop happen in the same cycle?A push is accepted only when not full and a pop only when not empty. When both are accepted, count stays the same; push alone adds one; pop alone subtracts one. Decide explicitly whether a push is allowed on a full FIFO in a cycle that also pops. Revisit Simultaneous push and pop.
The write response may only be given after both the write address and the write data handshakes have happened. The slave must wait for the W handshake (and use its data and strobes) before asserting BVALID. Revisit Responses, strobes and errors.