Memory & Buses

What this section covers

On-chip memory and standard buses connect datapaths to software and peripherals . This section covers inference rules, flow control, and AXI family basics used in block and SoC integration.

Topics in this section

1. SRAM/ROM inference — templates and portability

2. Register files — multi-port read/write

3. Valid/ready — skid buffers and backpressure

4. AXI-Lite — register peripheral protocol

5. AXI-Stream — streaming data plane

6. Bus integration — address map and bridges

Valid/ready slice

producer ──valid/ready──► consumer
    │                           │
 optional skid buffer when ready falls

Key takeaways

• Valid/ready is the on-chip micro-protocol — appears in FSMs and CDC.

• AXI naming is verbose but regular — map signals to FSM states.

• Register file ports drive arbitration and timing in hot paths.

Related topics

• Tri-state & buses

• Memory controller FSM

• Stalls & bubbles

• Memory/buses interview

Deep dive

This lesson deepens Memory & Buses within memory-buses. Senior reviewers expect you to connect mechanism to memory inference, valid/ready, and AXI family protocols — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: protocol assertions, backpressure tested. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

MEMORY & BUSES

  inputs ──► [memory-buses] ──► mechanism ──► outputs
                │                │
           memory-buses     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// memory-buses/memory-buses: Memory & Buses
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Skid buffer vs FIFO on valid/ready?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Memory & Buses": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Memory & Buses : Register file read-after-write hazard — bypass or document latency.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// AXI beat checker
assert (valid && ready) |-> stable_data;

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Memory & Buses". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.