Memory and bus questions test interface discipline. Every strong answer names the rule, the reason, and the evidence.
Rule | One line |
|---|---|
Handshake | No transfer without valid and ready together; the payload stays still until then. |
Backpressure | Any channel may stall with ready. A design that cannot tolerate that will hang. |
Storage | Small multi-ported arrays may favor flops; bulk tables often favor compatible RAM. Check target, ports, latency and PPA. |
Decode | No address falls through. A fabric-level hole answers with an error, never with OKAY; reserved offsets inside a slave follow that slave's documented policy. |
4 lessons, about 23 min
Valid and every payload bit stay exactly as they were until the handshake cycle. The source advances only after ready joins valid.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
The valid/ready contract
A transfer happens when valid and ready are both high in the same cycle.
Once valid is high, valid and payload hold until the handshake. Only ready may move freely.
A link that never stalls still needs the stability checker, or the bug appears the day one stalls.
Rule of thumb: valid stays up and data stays still until ready answers.
AXI backpressure and deadlock risk
Each channel has its own valid/ready, yet a write response needs both the accepted address and all the data.
A master must offer each VALID without waiting for READY. A slave may wait for both offers before READY.
Every address consumes an outstanding slot until its response returns. Dropped responses fill the table and stall the master.
Rule of thumb: every channel can say not ready, so no side may wait on another channel's READY before offering VALID.
Register file vs SRAM
A small, highly multi-ported file with combinational reads suits flops and muxes. A larger low-port array suits SRAM.
There is no universal size crossover. Compare macros, banking, latency and measured area, timing and power.
Same-cycle read-after-write has three honest answers: forward, return the old word, or stall. Never leave it undefined.
Rule of thumb: pick the structure from ports and latency, then write down what a collision does.
Unmapped addresses, decode errors and SLVERR
Every address decodes to exactly one slave or to the default slave. The default slave answers with an error, never OKAY.
The interconnect returns DECERR for an address it cannot decode. A selected slave reports its own failure as SLVERR.
Keep one central map. Per-slave decoders drift apart and leave gaps and overlaps.
Rule of thumb: a hole in the address map must produce an error response on the first access.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: Two-stage valid/ready pipeline: backpressure and skid buffers
Code lab: AXI stream handshake
Practice question: Waveform debug: a write transaction timeout
Practice question: Single-port register file, parameterised depth and width
Code lab: A 2x8 register file
Interview: run a mock interview on this topic