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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
      • Why scan exists
      • The scan chain at RTL abstraction
      • Test-mode integration checklist
      • Controllability and observability in practice
      • Fault Coverage by Hand
    • Physical Awareness Hub
    • Waveform Debug Hub
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
  • Glossary and Notation
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‹Senior & Interview
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. DFT and Scan Hub

Part 9 · Senior · Senior

DFT and Scan Hub

Scan makes chip internals testable: why it exists, the chain model, integration, and observability.

  • 5topics
  • 5lessons

Topics in this section

  1. 1Why scan exists1 lesson
  2. 2The scan chain at RTL abstraction1 lesson
  3. 3Test-mode integration checklist1 lesson
  4. 4Controllability and observability in practice1 lesson
  5. 5Fault Coverage by Hand1 lesson
On this page

    Manufacturing test requires forcing internal states and observing internal effects. Scan converts sequential logic into a chain of controllable and observable storage elements.

    Idea

    Meaning

    Where it is covered

    Controllability

    Test logic can drive an internal node to 0 and 1

    Why scan exists

    Observability

    A node effect can propagate to a scan-out or a primary output

    Controllability and observability in practice

    Test mode

    Clocks, resets, and constraints stay deterministic while shifting

    Test-mode integration checklist

    Scan chain

    Muxed-D flops stitched si-to-so, shifting vectors in and out

    The scan chain at RTL abstraction

    Scan operation as shift in, capture, and shift out.
    Shift loads a vector, one capture cycle applies it to the logic, and shift-out reads the response.

    Lessons in this topic

    5 lessons, about 24 min

    1. 1Why scan existsYou can explain why scan gives access to deep state, name what ATPG needs from the RTL, and say when scan does not help.4 min
    2. 2The scan chain at RTL abstractionYou can build a scan flop and a four-flop chain, follow shift, capture and shift-out, and estimate the time of a scan operation.6 min
    3. 3Test-mode integration checklistYou can add a test-mode bypass to a clock enable, handle X sources and resets for test, and order the checks when ATPG coverage is low.3 min
    4. 4Controllability and observability in practiceYou can shorten a wait in test mode only, make a rare event sticky, and explain why a guard signal never gets a test override.3 min
    5. 5Fault Coverage by HandYou can list the stuck-at faults of a small circuit, decide whether a pattern detects one, compute fault and test coverage from a simulation, and explain why a redundant fault is untestable.8 min
    Check yourself Why does a passing functional testbench not prove a chip is manufacturable?

    Functional patterns check behaviour the designer thought of. Manufacturing test must also catch defects the designer never modelled, which needs direct control and observation of internal state.

    Interview

    Expect “why scan” as an opener. The strong answer names controllability and observability, then connects them to shift, capture, and the integration checklist in the later lessons.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Why scan exists

    • A scan flop has a mux in front: scan_en = 1 takes the previous flop, scan_en = 0 takes the functional input.

    • ATPG treats each capture cycle as combinational logic between scan flops.

    • Scan improves access, not coverage. Untestable logic stays untestable until the RTL gives the tool a path to it.

    Rule of thumb: scan adds a second way to reach the same state; it does not change the function.

    The scan chain at RTL abstraction

    • A scan flop is a D flop with a 2:1 mux; the first bit shifted in ends in the last flop, and is the first bit out.

    • A scan operation costs about (longest chain + capture cycles) x patterns, plus one final unload.

    • scan_en must be quasi-static for stuck-at and launch-off-capture tests; a glitch corrupts the vector.

    Test-mode integration checklist

    • OR the functional enable with test mode so shifting never depends on functional activity.

    • Masking hides an X but does not remove its source; record every mask as a coverage hole.

    • Debug low coverage in order: unconstrained inputs, masked X sources, un-overridable clocks, then the chain.

    Controllability and observability in practice

    • A test-mode override may shorten a delay; it must change nothing when test mode is low.

    • A sticky flag latches the first pulse until reset, so a later shift-out sees it.

    • Never override a signal whose name carries a guard: allow, grant, secure, lock, privilege.

    Rule of thumb: shorten delays in test mode, never bypass permission checks.

    Fault Coverage by Hand

    • A pattern detects a fault only when it activates the net to the opposite value and the difference propagates to an observed output.

    • Fault coverage divides by every fault; test coverage divides by the faults left after untestable ones are removed. Report both.

    • Scan turns flops into pseudo-inputs and pseudo-outputs, so the logic between flops can be tested like a combinational circuit.

    Rule of thumb: never accept a coverage number without the fault list it was divided by and a reviewed reason for every excluded fault.

    Practise it

    • Mini project: the capstone: a resilient streaming peripheral, stage by stage

    • Code lab: Scan chain stub

    • Code lab: DFT scan enable

    • Interview: run a mock interview on this topic

    PreviousNext: Why scan exists

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    See also

    • Low-Power RTL Hub
    • Physical Awareness Hub
    • Waveform Debug Hub