A gated clock that the tester cannot override stops its chain. The enable path needs a test-mode bypass so shifting never depends on functional activity.
The listing below is the enable half of that contract. It ORs the functional enable with test mode, which keeps the clock path alive while shifting.
`timescale 1ns/1ps
module test_clk_override (
input logic func_en_i,
input logic test_mode_i,
output logic eff_en_o
);
assign eff_en_o = func_en_i | test_mode_i;
endmoduleA chain can start unknown: shifting a complete known vector flushes its old contents after the chain length in edges. Capture must then start from the intended loaded state, with clocks, reset controls and any X sources handled by the test protocol.
Check | Rule | Failure without it |
|---|---|---|
| Propagate both signals explicitly to the inserted logic | Unstitched flops hold functional data mid-vector |
No un-overridable gated clocks | Every gate opens in test mode, as above | Dead chains wherever the enable is low |
Asynchronous resets reviewed | Keep resets inactive during ordinary shift and capture; apply reset tests as separate defined operations | An asserted reset prevents loading; a mid-shift reset destroys the vector |
X sources controlled or masked | RAM outputs, analog flags, and tied-off modes drive known values | Unknowns spread and invalidate the whole response |
High. The OR in the listing decides it: test mode holds the path open regardless of the functional enable.
Capture becomes unknown wherever the X spreads, so the response mismatches. Control the RAM (bypass or init) or mask the path in test mode.
The enable override plus an X-source mask, checked over every combination of their inputs.
`timescale 1ns/1ps
module test_clk_override (
input logic func_en_i,
input logic test_mode_i,
output logic eff_en_o
);
assign eff_en_o = func_en_i | test_mode_i;
endmodule
module test_x_mask (
input logic flag_i,
input logic test_mode_i,
output logic flag_o
);
assign flag_o = test_mode_i ? 1'b0 : flag_i;
endmodule