At senior level, low-power RTL starts with reducing needless switching. Clock gating is usually the highest-impact technique because it stops flop toggles directly.
Technique | What it removes | Cost of getting it wrong |
|---|---|---|
Clock gating | Flop toggles in idle cycles | Runt pulses from ad-hoc |
Safe gating style | Glitch and test risk around each gate | Untestable domains without a scan override |
Isolation and retention | X spread from off domains and lost state | Corrupted control and failed restore |
UPF intent | Drift between RTL and implementation | Missing isolation or retention in silicon |
4 lessons, about 19 min
Clock gating driven by an idle condition. A testbench that counts gated edges against free edges shows the saved toggles, while the held state stays correct.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Clock gating done right
A data enable alone does not stop clock activity; gating the clock does. Leakage stays either way.
A raw clk & en can glitch if en changes while clk is high. The ICG latch closes during the high phase.
Write a plain enable and let the flow map it to a library ICG; instantiate a cell only for special cases such as a scan override.
Rule of thumb: never gate a clock with raw AND logic in RTL.
Safe gating style
The enable flop moves changes to just after the rising edge; the ICG latch, not the flop alone, protects the current pulse.
Every gate gets the test override, or a domain cannot shift.
Prefer one gate per functional cluster; finer gates add ICG, control and clock-tree cost that can cancel the saving.
Rule of thumb: if a gate has no scan override, its whole domain is dark in test.
Power domains, isolation and retention
Every OFF-to-ON crossing needs an isolation cell clamped to a safe value.
Quiesce, isolate, then open the switch. On wake, release isolation last, after power, restore and reset are ready.
Retain only state that cannot be rebuilt, such as context pointers; pipeline registers refill by themselves.
Rule of thumb: isolate before power drops, and release isolation only when the domain is ready.
UPF intent every RTL lead should know
UPF holds policy (domains, switches, isolation, retention, state tables); RTL stays clean and exposes the hooks.
For external capture, save before isolating; on wake, keep isolation on until restore and readiness are done.
Internal retention cells save local state and need not see the clamps.
Rule of thumb: the tools insert the cells, but RTL drives the sequence.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: A safe clock-gating cell with a latch-based enable
Code lab: Clock-gate control FSM
Practice question: Integrated clock gating (ICG) cell usage in RTL
Practice question: Design strategy for isolation cell enable control
Code lab: Isolation cell model
Interview: run a mock interview on this topic