Split the design into domains

Complex SoCs split logic into power domains so always-on logic can survive while optional domains power down.

Crossings between domains need isolation and sometimes level shifters. Even where insertion is automated, RTL must carry clear boundary intent and clean handshake behavior.

Read it from the power controller outwards: it is the only block that must stay powered to switch the other domain off and on.

• Switch enable connects or removes VDD_SW, the supply of everything inside the dashed box.

• iso sits where the accel outputs enter live logic. With iso_en high it drives a fixed value, so a dying domain cannot send X onward.

• Save and restore move context into a register that keeps the always-on supply, so it survives while VDD_SW is off.

Clamp every crossing

Signals leaving an OFF domain must not float into live logic. An isolation cell clamps each crossing to a chosen safe value while isolation holds.

Watch clamped_out: it follows off_data until iso_en rises, then it stays 0.

• Slot 0: iso_en is 0, off_data is 1, and the output is 1.

• Slot 1: off_data is 0, and the output follows to 0.

• Slot 2: iso_en is 1, and the output clamps to 0 although the input is 1.

• Slot 3: the input floats (x), and the output stays 0.

• Slot 4: the input is still x, and the output is still 0.

• Slot 5: iso_en is 0, the input is 1, and the output follows again.

Quiesce, then switch

Power switches move only after the boundary is quiet. RTL owns this order even when tools insert the cells.

1. Drain traffic and park every interface in idle.

2. Assert isolation on each OFF-to-ON crossing.

3. Open the switch only after isolation acknowledges.

4. On wake, restore power and wait for synchronized power-good; complete retention restore and reset/clock readiness while isolation remains asserted; only then release isolation and resume traffic.

Retention is used for state that must survive power collapse (context pointers, security state, protocol epoch). Separate retained and reconstructable state early in architecture.

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// snippet: retention save and restore idiom (partial; the always-on side owns the saved copy)
always_ff @(posedge clk_aon or negedge rst_aon_n) begin
  if (!rst_aon_n)
    ctx_ptr_q <= '0;
  else if (save_ctx_i)
    ctx_ptr_q <= ctx_ptr_d;
end

Common mistakes

Testbench

Clamp-0 and clamp-1 cells with the testbench that proves pass-through, clamp, X blocking, and release.

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`timescale 1ns/1ps
module iso_clamp0 (
  input logic iso_en, off_data,
  output logic clean
);
  assign clean = iso_en ? 1'b0 : off_data;
endmodule

module iso_clamp1 (
  input logic iso_en, off_data,
  output logic clean
);
  assign clean = iso_en ? 1'b1 : off_data;
endmodule

Related topics

• UPF intent every RTL lead should know