RTL is not complete when simulation passes. It is complete when synthesis, STA, CDC/RDC, power, DFT, equivalence, and physical implementation agree on the same design intent and every exception has an owner.
A packet-checksum block supplies the worked closure case. A candidate adds a partial-sum stage to address setup timing, changing latency, logical equivalence checking (LEC) alignment and placement. The dossier below uses invented planning values, not measured results.
5 lessons, about 21 min
Area, power, hold, congestion, CDC, equivalence, latency, and functional regression may have worsened. Closure compares a controlled multi-metric baseline.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Ownership and Handoff
The RTL owner updates the latency contract and handoff manifest; STA, physical design, verification and LEC each own their part.
Every waiver has a reason and an expiry; every black box has a model or a risk owner.
Interface latency, reset, clock, power and test-mode assumptions are part of the handoff.
Reproducible QoR
Use identical parameters, constraints, libraries, tool version and physical seed before weighing timing against area, power, hold and congestion.
Repeat representative seeds; one favourable seed does not show robustness.
Prove the runs are comparable before calling the delta an RTL improvement.
Equivalence-Friendly RTL
Sequential equivalence compares behaviour across cycles, not internal registers.
Outside reset, C1.valid[k] = C0.valid[k-1], and the tag and sum match one cycle later.
Review every unmatched point; never waive by pattern alone. Assumptions are part of the proof.
ECO Regression and Release
Freeze the baseline, find the cause, make the smallest change, and rerun every check the change can affect.
Compare all modes, corners and neighbouring paths, not only the original violation.
Record the change, evidence, residual risks, waivers, approvals and rollback point.
Proving an ECO: Equivalence and Gate-Level Simulation
Fix the RTL and the netlist separately, then prove one against the other. Every compare point must be proven, and the run must fail on any that is not.
An unproven point names the cone to debug; a miter and a SAT counterexample give the input that shows the difference.
Before trusting a pass, count compare points and look for inputs paired as constants. A constant on a functional input proves a different design.
Rule of thumb: no ECO is done until LEC shows zero unproven points with no unexplained constants, and a short GLS run covers reset and the changed function.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Code lab: Cache tag compare
Interview: run a mock interview on this topic