Two's complement

The signed number format where the top bit has weight −2ⁿ⁻¹; the same adder works for signed and unsigned.

Representation drives behavior

Sign extension

Widening a signed value by copying its top bit; zero extension copies 0 and is for unsigned values.

Sign and zero extension

Overflow (V) and carry (C)

Carry is the unsigned out-of-range answer; overflow is the signed one. They are independent, most visibly for subtraction.

First project: a 4-bit ALU

Fixed point (Qm.n)

An integer read with an implied binary point: m integer bits and n fraction bits.

The fixed-point contract

Saturation

Clamping a result to the largest or smallest representable value instead of letting it wrap.

Saturation policy

Levels of logic

The number of gates on the longest path between two registers; it sets the minimum clock period.

Propagation delay and levels of logic

Blocking (=) and nonblocking (<=)

Blocking assigns now, in order; nonblocking schedules the update for the end of the time step. Use = in always_comb, <= in always_ff.

always_ff and always_comb

always_comb / always_ff

SystemVerilog process kinds that state intent: combinational logic, or flops clocked by an edge. Tools check that the code matches.

always_ff and always_comb

Unsized literal

A number without a width, such as 10 or 'd10. It is at least 32 bits wide and can widen a whole expression.

Binary and hexadecimal habits

Arithmetic shift (>>>)

Shift right that copies the sign bit, only for signed operands. It rounds toward minus infinity, unlike /.

Barrel shifter and rotate

Inferred latch

Storage created when a combinational block does not assign an output on every path.

Why accidental latches happen

parameter / localparam

A parameter is overridable per instance; a localparam is derived and cannot be overridden.

Parameters vs localparams

Generate block

A for or if construct that elaborates hardware copies at compile time; name it (gen_x) for stable hierarchy paths.

Generate loops and conditionals

Interface / modport

A bundle of signals passed as one port; a modport gives each side its own directions.

Interfaces, modports and portability

Clock enable

A mux in front of D that makes the flop reload its own value; the clock itself is untouched.

Clock enable vs gated clock

Throughput / latency

Results per cycle versus cycles from an input to its result. Pipelining raises the first and costs the second.

Throughput and latency

Valid/ready handshake

A transfer happens on a clock edge where valid and ready are both high; valid must not wait for ready.

Valid/ready pipeline flow control

Skid buffer

A small buffer that accepts the word arriving while ready drops, so the ready path can be registered.

Skid buffer and pipeline stages

Stall / bubble / flush

Hold a stage, insert an empty slot, or discard wrong-path work.

Structural hazards and stall logic

Forwarding (bypass)

Feeding a result straight to a waiting stage before it is written back.

Data hazards and forwarding

Retiming

Moving registers across logic to balance stage delays without changing cycle behaviour at the ports.

Retiming: the mechanism

LFSR

A shift register with XOR feedback; it generates pseudo-random sequences (PRBS) cheaply.

LFSR for PRBS generation

Moore / Mealy

Moore outputs depend only on the state; Mealy outputs also depend on the inputs and can react in the same cycle.

Moore and Mealy: the difference

One-hot / binary encoding

One flop per state versus the fewest flops; one-hot usually decodes faster.

Encodings compared

Illegal state

An encoding that is not a defined state; a default case item should recover from it.

Illegal states and recovery

Controller / datapath

The split between the FSM that decides and the registers and arithmetic that compute.

The controller/datapath split

Setup / hold

Data must be stable for a setup time before the capturing edge and a hold time after it.

Core equations and slack

Slack

Required time minus arrival time; negative slack is a violation.

Core equations and slack

Skew / jitter / uncertainty

Difference in clock arrival between flops; cycle-to-cycle edge variation; the margin STA subtracts for both.

Skew and jitter in practical STA

Corner

A process, voltage and temperature combination; signoff checks setup and hold at several.

Corners

SDC

Synopsys Design Constraints: the Tcl commands that tell STA about clocks, I/O delays and exceptions.

The SDC starter set

Multicycle / false path

Exceptions: a path allowed more than one cycle, or a path STA must not time at all.

Exception taxonomy

ICG

Integrated clock-gating cell: a latch plus AND that gates a clock without glitches.

The ICG cell

OCV / AOCV

On-chip variation: derates that make launch and capture paths slower or faster than nominal.

OCV and AOCV

Async assert, sync deassert

Reset enters immediately and leaves on a clock edge through a reset synchronizer.

The template

Recovery / removal

The setup and hold checks for a reset's release relative to the clock.

Recovery, removal and verification

Metastability

A flop that samples a changing input can take extra time to settle to 0 or 1.

What metastability means

MTBF

Mean time between synchronizer failures; set by settling time, τ, toggle rate and clock rate.

When to use 3FF

2FF synchronizer

Two flops in the destination domain that give a single bit time to settle.

2FF synchronizer baseline

Gray code

A count where one bit changes per step, so a crossing sees either the old or the new value.

Gray-code counter

Async FIFO

A dual-clock FIFO with Gray pointers; the standard way to move multi-bit data across domains.

Why async FIFOs

Toggle synchronizer

Turns an event into a level change that survives a slow destination clock.

Pulse synchronizers and toggles

RDC

Reset domain crossing: a path from logic reset by one reset to logic reset by another.

RDC is CDC plus reset asymmetry

Read-first / write-first

What a RAM returns when one address is read and written in the same cycle: old or new data.

Read-first vs write-first

AXI-Lite

A simple AXI subset: five channels, one transfer per transaction, no bursts.

AXI-Lite channel overview

AXI-Stream (TLAST, TKEEP)

A valid/ready data stream; TLAST marks a packet's end and TKEEP its valid bytes.

Packets, TLAST and TKEEP

CSR / W1C

Control and status register; write-1-to-clear is the usual access type for status bits.

Field access types

Byte strobes

Per-byte write enables (WSTRB) for partial writes.

Byte strobes and partial writes

SECDED

An ECC code that corrects single-bit and detects double-bit errors.

SECDED encode and syndrome

Self-checking testbench

A bench that compares against a reference and prints PASS or FAIL itself.

Self-checking and observability

Mutation (planted bug)

A deliberately broken design run to prove the bench can fail.

First project: a 4-bit ALU

Immediate / concurrent assertion

A check at one point in procedural code, or a property evaluated on clock edges over time.

Immediate vs concurrent assertions

assume / assert / cover

Constrain the environment, check the design, prove a scenario is reachable.

assert, cover and assume

Vacuous pass

A property that passes only because its trigger never happened; covers catch it.

Assumption discipline

Lint / waiver

Static rule checks on RTL; a waiver records a reviewed exception.

Lint, RDC and waiver policy

Scan / ATPG

Turning flops into a shift chain so test patterns can set and observe every one; ATPG generates the patterns.

Why scan exists

LEC

Logical equivalence checking: proves two netlists (or RTL and netlist) compute the same functions.

Equivalence-friendly RTL

ECO

Engineering change order: a late, minimal change to a netlist instead of a full re-run.

ECO levers

Isolation / retention

Clamping a powered-down domain's outputs; keeping chosen state through power-off.

Power domains and isolation

_q

Register output (the flop's Q)

count_q, state_q

_d or _next

Next value computed by combinational logic, loaded at the next edge

count_d, next_state

_n

Active-low signal

rst_n (reset is active when 0), arst_n for an asynchronous one

_sync

A value after a synchronizer, safe to use in the destination domain

req_sync

u_

Instance name prefix

u_fifo, u_gate

gen_

Named generate block

gen_stage[2].q

8'hF0, 4'b1011, 'd10

Sized hex and binary literals; an unsized literal is at least 32 bits

8'hF0 is 240 unsigned, −16 signed

logic signed [7:0]

Signedness is part of the declaration; without signed a vector is unsigned

$signed(x) reinterprets, it does not convert

[DW-1:0], [N-1:0]

Vectors run from the most significant bit down to 0

data[31:0]

The timescale directive, 1ns/1ps

Every bench uses 1 ns time units with 1 ps precision

#5 clk = ~clk; is a 10 ns, 100 MHz clock