Between two clock edges a signal must leave the launching flop, pass through the logic, and be stable at the capturing flop before the next edge. The capturing flop needs its setup margin too.
In one inequality:
Term | Meaning | Who controls it |
|---|---|---|
t_clk→q | Delay from clock edge to the launching flop's output | The cell library |
t_logic | Sum of gate and wire delays in the logic | Your RTL |
t_setup | How early data must arrive before the capture edge | The cell library |
t_uncertainty | Clock skew, jitter and margin | Clock design and constraints |
A design at 500 MHz has T = 2.0 ns. Suppose t_clk→q = 0.15 ns, t_setup = 0.10 ns and t_uncertainty = 0.15 ns. That leaves
If a typical gate plus its wire costs about 80 ps in this technology, the logic can be roughly 20 levels deep.
Read the bar from left to right: it is one clock period, from the launch edge to the capture edge.
Only the wide blue block is yours. The library fixes clk-to-Q and setup, and the clock design fixes uncertainty.
The thin pieces still cost 0.40 ns. That is 20 percent of the period before any logic runs.
The row of 20 ticks is the 1.6 ns divided by an 80 ps gate and wire. Each tick is one level of logic.
The numbers change from process to process, but the habit does not: convert the clock period into a logic-level budget before you design the block.
Gate delays depend on the cell, the load it drives (fan-out) and the wire. The 80 ps figure above is illustrative. Always use the delays from your own library and timing report for real decisions.
Structure | Approximate depth | Comment |
|---|---|---|
2:1 mux | 1–2 | One select-controlled gate pair. |
N:1 mux | ⌈log₂ N⌉ stages | A tree of 2:1 muxes. |
AND/OR of N inputs | ⌈log₂ N⌉ | A balanced tree, if the tool restructures it. |
Ripple-carry adder, N bits | ≈ N | Carry passes through every bit. |
Tool-built fast adder, N bits | ≈ log₂ N | Carry-lookahead or prefix structure. |
N-input priority chain (if/else) | ≈ N if built literally | Each condition waits for the one before it. |
Counting levels without load. A gate driving a large fan-out or a long wire is slower than the typical figure. Ten levels can cost more than twenty light ones.
Leaving out uncertainty. A budget of clock-to-Q plus setup only, with no skew and jitter margin, looks fine on paper and fails in the timing report.
T = 1/800 MHz = 1.25 ns. Logic budget = 1.25 − 0.12 − 0.08 − 0.10 = 0.95 ns.
Each stage holds less logic, so the clock period can shrink. Without stalls the elapsed latency is stages times the operating period. Balance and register overhead matter, so it often grows slightly. The later pipelining example rises from 6.3 ns to 6.6 ns from one to two stages. Throughput stays one result per cycle, but the cycle is shorter, so results per second rise (159 to 303 million per second in the later example) while latency in cycles grows.