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Course contents

  • RTL Foundations36
  • Combinational Design25
    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
    • Arithmetic Blocks
    • Comparators and Shifters
    • Tri-State and Shared Buses
    • Latch Inference
    • Arithmetic Datapaths
      • Fixed-Point Contract
      • Width Growth
      • Rounding and Quantization
      • Saturation Policy
      • Divider Architectures
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹Combinational Design
  1. Topics
  2. RTL Design
  3. Combinational Design
  4. Arithmetic Datapaths

Part 2 · Combinational · Advanced

Arithmetic Datapaths

Fixed-point representation, width growth, rounding, saturation and division. The pipelined MAC and its precision verification continue in Sequential, under Pipelining.

  • 5topics
  • 5lessons

Topics in this section

  1. 1Fixed-Point Contract1 lesson
  2. 2Width Growth1 lesson
  3. 3Rounding and Quantization1 lesson
  4. 4Saturation Policy1 lesson
  5. 5Divider Architectures1 lesson
On this page

    Real datapaths need more than an operator. They need a numeric contract: signedness, binary-point position, intermediate widths, rounding, saturation, latency, throughput, and an error budget.

    A single worked design runs through the topic: a signed sensor pipeline multiplies two 16-bit fractional samples, accumulates 1024 products, and returns a 16-bit result. Each lesson makes one decision for that same pipeline, so the final verification plan checks one coherent numeric contract.

    The baseline sums, rather than averages, 1024 Q1.15 products. It retains F=30 through the 42-bit accumulator, then drops 15 fractional bits with nearest-even rounding and clamps to signed Q1.15. For an unclipped frame the output-quantization error is at most half an output LSB, 2^-16, relative to the exact sum of the stored input samples. Clipped frames are flagged and checked separately; that error bound does not cover clipping or input-sampling error.

    Lessons in this topic

    5 lessons, about 17 min

    1. 1Fixed-Point ContractYou can read and write QI.F formats, align binary points before adding, and predict the fractional bits of a product.3 min
    2. 2Width GrowthYou can compute the full-precision width of sums, products and accumulators, and write RTL that extends operands before the operation.2 min
    3. 3Rounding and QuantizationYou can choose a rounding policy, handle negative ties, and implement a signed nearest-even quantizer from the floor quotient and remainder.6 min
    4. 4Saturation PolicyYou can round wide, clamp to the output range, then narrow, and compute the limits for a signed output of any width.3 min
    5. 5Divider ArchitecturesYou can compare divider architectures, trace a restoring division step by step, and list the corner cases every divider must handle.3 min
    Check yourself Why is logic signed [15:0] sample incomplete as a numeric specification?

    It gives storage width and signedness but not binary-point position, allowed range, rounding, overflow policy, or the width expected for intermediate operations.

    Tip

    Write the numeric contract beside the interface before writing operators: input/output formats, full-precision widths, quantization point, overflow policy, latency, throughput, and reference model.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Fixed-Point Contract

    • QI.F has total width I + F, with I including the sign bit. The stored code x means x / 2^F.

    • Addition needs aligned binary points. A product has F1 + F2 fractional bits.

    • A right shift changes scale but does not define rounding or overflow. Name both at every narrowing step.

    Rule of thumb: write the format of every signal, including the sign-bit convention.

    Width Growth

    • Extend operands to the intended result width before adding, and store a product in a full-width signed destination.

    • Accumulating 1024 terms adds 10 growth bits: 32 + 10 = 42.

    • Fewer bits need a bound that you assert and model, not an assumption.

    Rounding and Quantization

    • Write C = q * 2^F + r with q = floor(C / 2^F), so 0 <= r < 2^F even when C is negative.

    • Nearest-even increments q when r > 2^(F-1), or when r equals 2^(F-1) and q is odd.

    • Quantize once at a deliberate boundary and keep guard bits before it.

    Rule of thumb: document whether ties go away from zero, toward zero, or to even.

    Saturation Policy

    • Wrap for addresses and counters. Saturate for signal and control values.

    • Compare the extended full-precision value with the limits, then narrow.

    • Signed limits: maximum is 0 followed by W-1 ones, minimum is 1 followed by W-1 zeros.

    Rule of thumb: round wide, clamp, then narrow.

    Divider Architectures

    • A restoring divider shifts in one dividend bit per step and subtracts the divisor if the trial remainder is large enough (13 / 3 gives 4 remainder 1).

    • Divide by zero and the most negative value divided by -1 need explicit behaviour.

    • Iterative suits infrequent control updates; a pipeline suits one sample per cycle.

    Rule of thumb: inspect what / synthesises into, or instantiate a divider you designed.

    Practise it

    • Mini project: a 32-bit leading-zero counter and normaliser

    • Code lab: Build saturation logic

    • Practice question: A restoring divider in detail

    • Practice question: A non-restoring divider

    • Interview: run a mock interview on this topic

    PreviousNext: Fixed-Point Contract

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    Up nextFixed-Point Contract

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    See also

    • Combinational Timing Overview
    • Muxes, Decoders and Encoders
    • Arithmetic Blocks