RTL Foundations

What this section covers

Before you pipeline a datapath or close timing on an FSM, you need crisp fluency in logic algebra , bit-level arithmetic , and synthesizable HDL style . This section builds that base so later parts — combinational blocks, sequential pipes, CDC — land on solid ground.

Each topic is a rich hub plus 7–8 sub-lessons with theory, ASCII diagrams and charts, runnable Verilog/SystemVerilog examples, takeaways, pitfalls, and cross-links.

Topics in this section

1. Digital Logic — Boolean algebra, De Morgan, truth tables, K-maps, implementation trade-offs.

2. Number Systems — binary/hex, two's complement, extension, overflow.

3. Verilog Core — modules, assign vs always, blocking vs non-blocking.

4. Operators & Types — width rules, concat, reductions, parameters.

5. SystemVerilog RTL — logic, always_ff/comb, enums, interfaces.

6. Simulation & TB — clock/reset, self-checking, debug patterns.

RTL learning stack (this section = bottom layer)

RTL DESIGN STACK — foundations support everything above

  Part 9  Senior / interview
  Part 8  Advanced (generate, lint, SVA, formal)
  Part 7  Memory & buses
  Part 6  Reset & CDC
  Part 5  Timing & clocking
  Part 4  FSM & control
  Part 3  Sequential design
  Part 2  Combinational design
  ─────────────────────────────
  Part 1  FOUNDATIONS  ← you are here

Key takeaways

• Foundations are not 'review' — width, signedness, and latch inference bite senior engineers daily.

• Work topics in order; revisit number systems when you hit arithmetic and pipelining.

• All Part 1 topics use hub + sub-lesson nesting under rtl/foundations/<topic>.

Related topics

• Combinational overview (next section)

• Number systems

• Verilog fundamentals

• Latch inference (Part 2)

• Combinational interview Q&A

Deep dive

This lesson deepens RTL Foundations within foundations. Senior reviewers expect you to connect mechanism to HDL fluency, width, and simulation habits — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: lint clean, self-checking TB, width documented. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

RTL FOUNDATIONS

  inputs ──► [foundations] ──► mechanism ──► outputs
                │                │
           foundations     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// foundations/foundations: RTL Foundations
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Explain blocking vs non-blocking with a flop example.

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "RTL Foundations": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for RTL Foundations : You inherit a module with mixed blocking/non-blocking assigns. List every signal, classify comb vs seq, rewrite with always_comb/ff.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Corner-case TB fragment
initial begin
  for (int i = 0; i < 256; i++) begin
    drive(i[7:0]);
    @(posedge clk);
    check(ref(i[7:0]), dut_out);
  end
end

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "RTL Foundations". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.