Foundations cover logic algebra, number representation, Verilog and SystemVerilog, and self-checking testbenches. Later combinational and sequential design assumes all four; no prior hardware experience is assumed beyond reading code and thinking in binary.
Topic | Lessons | After it you can… | Study time |
|---|---|---|---|
6 | Simplify equations, apply De Morgan, and judge the cost of logic. | 2–3 h | |
6 | Work with two's complement, signedness, extension and overflow flags. | 3 h | |
6 | Write modules, the two process templates, and use | 3 h | |
6 | Control widths, slices, concatenation, reductions, shifts and parameters. | 3 h | |
6 | Use | 2–3 h | |
6 | Build self-checking tests and define when a block is done. | 3 h |
Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.
Unfamiliar term or naming suffix? The Glossary and notation page defines each in one line and links to the lesson that teaches it.
New readers can skip this checkpoint until they finish the six topics. Returning readers can use it to choose what to revisit; these are outcomes, not entry requirements.
8'hF0 as signed and unsigned? Why does $signed(a) + b sometimes give the wrong answer? What does always_comb check that always @(*) does not?8'hF0 is 240 unsigned and −16 signed. If b is unsigned, the whole expression is unsigned, so $signed(a) is treated as unsigned and zero-extended: its sign is lost. always_comb infers its sensitivity (including reads inside called functions), runs once at time 0, forbids other processes from writing its variables, and lets tools flag an inferred latch. If any of them is shaky, revisit Representation drives behavior, Sign and zero extension and always_ff and always_comb.
Runnable examples. Authors compile complete examples with node scripts/tools/check-rtl-snippets.mjs rtl/foundations and execute self-checking benches with node scripts/tools/run-rtl-testbenches.mjs rtl/foundations. These are separate author checks, not part of every build. Partial snippets and deliberately broken examples are marked and skipped. You can reproduce a printed PASS line with iverilog -g2012.
Check-yourself questions. Each lesson ends with check-yourself questions; attempting them before reading the explanation measures understanding.
Scratch testbench. A tiny tb module for trying expressions and printing results demonstrates the language rules faster than reading about them.