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Course contents

  • RTL Foundations57
    • Digital Logic for RTL Engineers
    • Number Systems for RTL Engineers
      • Representation Drives Behavior
      • Binary and Hexadecimal Conversion Habits
      • Two's Complement Intuition
      • Sign Extension, Zero Extension and Casting
      • SystemVerilog Signed Arithmetic Pattern
      • Overflow Detection Patterns
      • Unsigned and Signed Overflow Flags
      • Number Systems Summary
      • Worked Examples and Waveforms
    • Verilog Fundamentals
    • Verilog Operators and Types
    • SystemVerilog for RTL
    • Simulation and Testbenches
  • Combinational Design58
  • Sequential Design61
  • FSM & Control66
  • Timing & Clocking64
  • Reset & CDC58
  • Memory & Buses94
  • Advanced RTL60
  • Senior & Interview175
  • Glossary and Notation
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‹RTL Foundations
  1. Topics
  2. RTL Design
  3. RTL Foundations
  4. Number Systems for RTL Engineers

Part 1 · Foundations · Beginner

Number Systems for RTL Engineers

Bits, hex, two's complement, signedness and width rules, and overflow flags for RTL.

  • 9topics
  • 9lessons

Topics in this section

  1. 1Representation Drives Behavior1 lesson
  2. 2Binary and Hexadecimal Conversion Habits1 lesson
  3. 3Two's Complement Intuition1 lesson
  4. 4Sign Extension, Zero Extension and Casting1 lesson
  5. 5SystemVerilog Signed Arithmetic Pattern1 lesson
  6. 6Overflow Detection Patterns1 lesson
  7. 7Unsigned and Signed Overflow Flags1 lesson
  8. 8Number Systems Summary1 lesson
  9. 9Worked Examples and Waveforms1 lesson
On this page

    A register holds bits, and declarations decide what they mean. Signedness and width decide comparison, shifts, extension and overflow.

    Same bits interpreted as unsigned or two's complement, with different ranges and overflow conditions.
    The bits never change; the meaning, the range and the overflow rule do.

    Lessons in this topic

    6 lessons, about 22 min

    1. 1Representation Drives BehaviorYou can state how a bit pattern is read as signed or unsigned, and predict the result of mixed-signedness expressions.3 min
    2. 2Binary and Hexadecimal Conversion HabitsYou can convert between binary and hex by nibbles and write sized Verilog literals with the right width, base and sign.4 min
    3. 3Two's Complement IntuitionYou can decode a two's complement value from its weights and explain why carry and signed overflow are different questions.5 min
    4. 4Sign Extension, Zero Extension and CastingYou can extend a value with the right fill bits, and write casts so that mixed signed and unsigned operands give the intended result.3 min
    5. 5SystemVerilog Signed Arithmetic PatternYou can write signed add and multiply with the right result width and narrow the result by truncating, saturating or flagging overflow.3 min
    6. 6Overflow Detection PatternsYou can derive carry and signed-overflow flags for add and subtract, and say which one matches the interpretation of the data.4 min
    Check yourself How many distinct values can an N-bit register hold, regardless of interpretation?

    Exactly 2ᴺ. Interpretation only changes which numbers those patterns stand for (0…2ᴺ−1 unsigned, or −2ᴺ⁻¹…2ᴺ⁻¹−1 signed).

    Interview

    “What is the range of an 8-bit signed number, and what happens when you negate the most negative value?” Both questions come back to two's complement; the answers are in the third lesson.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Representation Drives Behavior

    • Any unsigned operand makes the whole arithmetic or comparison expression unsigned.

    • The shift amount is the exception: it does not change the signedness of the shifted value.

    • >> never sign-extends; >>> on a signed operand keeps the sign, but it rounds toward minus infinity: -5 >>> 1 is -3, while -5 / 2 is -2.

    Rule of thumb: declare numbers signed and raw bit patterns unsigned, and cast explicitly between them.

    Binary and Hexadecimal Conversion Habits

    • One hex digit is four bits: group from the right and translate each group.

    • A sized literal is <size>'[s]<base><digits>. Write a negative value with a separate unary minus.

    • An unsized literal or bare 10 is at least 32 bits wide and can widen the whole expression.

    Rule of thumb: size every literal.

    Two's Complement Intuition

    • The top bit has negative weight. N bits cover -2^(N-1) to 2^(N-1) - 1.

    • Arithmetic is modulo 2^N: carry marks the unsigned boundary, signed overflow marks the signed one.

    • The most negative value has no positive counterpart. Negate, abs and saturate blocks must handle it.

    Rule of thumb: negate by inverting every bit and adding one, but sign-extend first if you need the exact result.

    Sign Extension, Zero Extension and Casting

    • Zero extension is correct for unsigned values and sign extension for two's complement values.

    • A concatenation is unsigned even when it copies the sign bit.

    • A cast changes interpretation, not bits. To mix operands, zero-extend the unsigned one into a wider signed type first.

    Rule of thumb: widen first with the fill you mean, then do the arithmetic in one signedness.

    SystemVerilog Signed Arithmetic Pattern

    • An add of two N-bit numbers needs N+1 bits and a multiply needs 2N.

    • In a direct assignment the wide destination sets the arithmetic width, but it cannot recover bits lost inside a narrow intermediate.

    • >>> divides a signed value by 2^k and rounds toward minus infinity: -5 >>> 1 is -3.

    Rule of thumb: narrow only at the end, and only on purpose.

    Overflow Detection Patterns

    • Carry is the unsigned flag. Signed overflow happens only when both operands have the same sign and the result sign differs.

    • For a - b, form a + ~b + 1: the carry means no borrow, and overflow needs operands of different signs.

    • The two flags are independent, so compute both from one verified module.

    Rule of thumb: pick the flag that matches how the bits are interpreted.

    Practise it

    • Mini project: a 4-bit ALU with flags and an exhaustive bench

    • Code lab: Build a signed comparator

    • Code lab: Build saturation logic

    • Interview: run a mock interview on this topic

    PreviousNext: Representation Drives Behavior

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    See also

    • Digital Logic for RTL Engineers
    • Verilog Fundamentals
    • Verilog Operators and Types