Unsigned and Signed Overflow Flags

Status register pattern

typedef struct packed {
  logic sticky_ovf;
  logic sticky_neg;
  logic sticky_zero;
} alu_flags_t;

always_ff @(posedge clk) begin
  if (alu_op_valid) begin
    if (ovf) sticky_ovf <= 1'b1;
    if (result == 0) sticky_zero <= 1'b1;
  end
  if (clr_flags) sticky_ovf <= 1'b0;
end

Saturation on overflow

wire signed [7:0] sat_sum =
  signed_ovf ? (a[7] ? 8'sd-128 : 8'sd127) : sum;

Key takeaways

• Sticky flags survive until clear — good for ISR polling.

• Saturation vs wrap is a product decision — document it.

Common pitfalls

• Clear-on-read vs sticky semantics confusing driver software.

• Saturation only on overflow path — test max positive + 1.

Deep dive

This lesson deepens Unsigned and Signed Overflow Flags within foundations. Senior reviewers expect you to connect mechanism to HDL fluency, width, and simulation habits — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: lint clean, self-checking TB, width documented. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

UNSIGNED AND SIGNED OVERFLOW FLAGS

  inputs ──► [foundations] ──► mechanism ──► outputs
                │                │
           number-systems     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

logic signed [7:0] a, b;
logic signed [8:0] sum_wide;
assign sum_wide = a + b;
wire ovf = (a[7]==b[7]) && (sum_wide[7]!=a[7]);

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Explain blocking vs non-blocking with a flop example.

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Unsigned and Signed Overflow Flags": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Extended design scenario

Scenario for Unsigned and Signed Overflow Flags : A signed compare returns wrong results above 127. Trace width and $signed usage; fix port types and TB.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Corner-case TB fragment
initial begin
  for (int i = 0; i < 256; i++) begin
    drive(i[7:0]);
    @(posedge clk);
    check(ref(i[7:0]), dut_out);
  end
end

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Unsigned and Signed Overflow Flags". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.

Extended theory

Foundations are the compression algorithm for the rest of the course: every multi-bit bus, FSM output, and STA report ultimately rests on whether you sized, signed, and simulated the bit-level behavior correctly.

For "Unsigned and Signed Overflow Flags", the invariant you defend in review is: behavior matches spec under all legal input sequences, reset flows, and backpressure patterns—not just the happy path shown in introductory diagrams.

Write the invariant as a comment above the module or as an SVA property when possible. Future you (and formal tools) will treat it as the contract.

Waveform reading guide

WAVEFORM NARRATIVE — Unsigned and Signed Overflow Flags

cycle 0: reset asserted, outputs safe/idle
cycle 1-2: reset held, clocks running
cycle 3: reset released, first legal inputs
cycle 4+: check output latency (N cycles)
mark FIRST mismatch cycle — not last

Second worked example

Alternate pattern emphasizing debug, coverage, or integration:

// Self-checking scoreboard pattern
class Scoreboard;
  int err;
  function void check(string name, logic [31:0] exp, act);
    if (exp !== act) begin
      $error("%s exp=%h act=%h", name, exp, act);
      err++;
    end
  endfunction
endclass

Comparison: naive vs production

NAIVE APPROACH              PRODUCTION APPROACH
quick hack, one sim vector    self-checking TB + corners
ignore lint warnings          zero new waivers
implicit widths               explicit casts/parameters
undocumented latency          latency in module header comment

Additional interview questions

• Explain Unsigned and Signed Overflow Flags to a verification engineer — what would they assert?

• What breaks first at high frequency or low voltage?

• What is your rollback plan if synthesis QoR is unacceptable?

• How would you debug this block with only a 32-bit GPIO trace?

Follow-up interview model answer

Q: What is the #1 mistake with Unsigned and Signed Overflow Flags?
A:
  MECHANISM: [core rule in one line]
  MOTIVATION: why teams care in tape-out
  PITFALL: what juniors do wrong
  EXAMPLE: one Verilog line or one waveform event

Hands-on lab part 2

1. Fork the worked example; add one assertion or SVA cover.

2. Inject a bug deliberately; confirm TB or assertion catches it.

3. Write 5-bullet PR description for your change.

4. Peer review: can a teammate enable the block without asking you?

Sign-off evidence checklist

• Directed sim log attached (PASS, seed noted)

• Lint report clean for touched files

• If sequential: reset + clocking section in README

• If bus-facing: protocol cheat sheet in module doc

• If timing-critical: note expected critical path endpoint