Advanced RTL

What this section covers

Production RTL is parameterized, lint-clean, and verifiable . This section covers generate loops, IP boundaries, synthesis constraints, coding rules, assertions, and when formal helps.

Topics in this section

1. Generate & parameters — scalable RTL

2. Hierarchy & IP — boundaries and reuse

3. Synthesizable RTL — what tools accept

4. Coding style & lint — team-wide rules

5. SVA for RTL — inline properties

6. Formal verification intro — bounded proofs

RTL quality pipeline

RTL ──► lint ──► synthesis ──► STA ──► formal (where valuable)
  │        │           │            │
generate  SVA        constraints   sign-off

Key takeaways

• Generate is not a free pass — elaboration time and debug complexity matter.

• Lint catches latch and width issues before sim — pair with Part 2.

• SVA and formal complement sim — especially for control and CDC assumptions.

Related topics

• RTL for timing

• Synthesizable RTL

• Coding style & lint

• CDC verification

• Waveform debug

Deep dive

This lesson deepens Advanced RTL within advanced. Senior reviewers expect you to connect mechanism to generate, lint, SVA, and formal hooks — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: waivers tracked, assertions on critical properties. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

ADVANCED RTL

  inputs ──► [advanced] ──► mechanism ──► outputs
                │                │
           advanced     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// advanced/advanced: Advanced RTL
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

When formal beats simulation for control logic?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Advanced RTL": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Advanced RTL : Generate loop out of memory — reduce unrolled depth or partition.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// SVA cover property for unreachable
cover property (@(posedge clk) state==ILLEGAL);

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Advanced RTL". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.