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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
    • Parameterization and Generate Hub
    • Top-Level Integration Hub
    • Synthesis Intent Hub
    • Style and Static Checks Hub
    • Assertions in RTL Hub
    • Formal Verification Basics Hub
    • Reusable SystemVerilog for RTL
  • Senior & Interview76
  • Glossary and Notation
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‹RTL Design
  1. Topics
  2. RTL Design
  3. Advanced RTL

Part 8 · Advanced · Advanced

Advanced RTL

Parameterized, reusable, lint-clean, verifiable RTL: SystemVerilog types, hierarchy, synthesis, assertions, and formal basics.

  • 7topics
  • 28lessons
On this page

    Production RTL is parameterized, lint-clean, and verifiable. This section covers generate loops, IP boundaries, synthesis constraints, coding rules, assertions, and when formal helps.

    Learning path through the advanced topics.
    Suggested order. It follows the quality pipeline RTL ──► lint ──► synthesis ──► STA ──► formal, adding proof where it pays.

    The seven topics

    Topic

    Lessons

    After it you can…

    Study time

    Parameterization and Generate

    3

    Write parameterized modules with generate loops and named overrides.

    25 min

    Hierarchy and IP Integration

    3

    Structure hierarchy with clean ports and propagated parameters.

    25 min

    Synthesizable RTL

    4

    Write inference-friendly RTL without latches or banned pragmas.

    25 min

    Coding Style and Lint

    3

    Apply style rules and run lint with disciplined waivers.

    25 min

    Assertions in RTL

    4

    Bind immediate and concurrent assertions with cover and assume.

    25 min

    Formal Verification Basics

    4

    Scope bounded proofs with sound assumptions on the right targets.

    25 min

    Reusable SystemVerilog

    7

    Use packages, packed types, parameter types, functions, and interfaces in portable RTL.

    2 h

    Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.

    Tip

    Run lint before simulating a new block. Width, latch, and clock findings are cheapest to fix before the testbench exists.

    Check yourself Why run lint before synthesis even when the testbench passes?

    The testbench samples behaviors while lint checks every path for width, latch, and rule violations. The Coding Style and Lint topic shows the rule table and waiver discipline.

    Interview

    Typical screening tasks from this section: parameterize a module with generate, explain parameter versus localparam and why defparam is banned, describe what synthesizes to flops versus RAM, name essential lint rules, write a handshake assertion, and explain bounded versus full proof.

    End-of-section checkpoint

    Use these four questions to decide whether you are ready to move on: explain, predict, implement and debug. If one is shaky, each answer names the lesson to revisit. New readers can skip this until they finish the section.

    Check yourself Explain: when do you use parameter and when localparam?

    A parameter can be overridden per instance, so it is the module's configuration interface. A localparam cannot be overridden; use it for values derived from parameters (widths, depths) so nobody can set them inconsistently. Revisit Parameters vs localparams.

    Check yourself Predict: assert property (@(posedge clk) req |-> ##[1:3] gnt); and req is high at cycle 0, with gnt first high at cycle 4. Pass or fail?

    Fail. The property needs gnt one to three cycles after req, that is at cycle 1, 2 or 3; cycle 4 is outside the window, so the assertion fails at cycle 3 when the window closes. Revisit Common RTL property templates.

    Check yourself Implement: build N identical register stages with a for generate loop. Why name the generate block?

    for (genvar i = 0; i < N; i++) begin : gen_stage ... end. The name gives each copy a stable hierarchical path (gen_stage[2].q) for waveforms, assertions, constraints and debugging. Revisit Generate loops and conditionals.

    Check yourself Debug: a formal run proves every assertion within seconds. You later find a real bug in that block. What is the most likely cause?

    An over-constraining assumption: for example, assuming a request never arrives while busy removes exactly the case with the bug, so the proof is vacuous. Check that cover properties for the interesting scenarios are reachable, and review every assume against the interface spec. Revisit Assumption discipline.

    Related topics

    • Previous: Memory & Buses

    • Next: Senior

    PreviousNext: Parameterization and Generate Hub

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    Up nextParameterization and Generate Hub

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    See also

    • RTL Foundations
    • Combinational Design
    • Sequential Design