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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub
    • Waveform Debug Hub
      • Debug hierarchy before touching code
      • Controlled dumps and trigger capture
      • Waveform bug patterns: latch and race
      • Handshake protocol violation
    • STA and ECO Hub
    • RTL-to-Implementation Closure
    • DFT-Ready RTL
    • Capstone: Resilient Streaming Peripheral
    • Principal Design Review
    • Senior RTL Interview Questions & Model Answers
  • Glossary and Notation
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‹Senior & Interview
  1. Topics
  2. RTL Design
  3. Senior & Interview
  4. Waveform Debug Hub

Part 9 · Senior · Senior

Waveform Debug Hub

Hierarchy-first RTL debug: reproduce, narrow by level, dump with control, and read latch, race, and handshake waves.

  • 4topics
  • 4lessons

Topics in this section

  1. 1Debug hierarchy before touching code1 lesson
  2. 2Controlled dumps and trigger capture1 lesson
  3. 3Waveform bug patterns: latch and race1 lesson
  4. 4Handshake protocol violation1 lesson
On this page

    Most debug time goes to searching, not fixing. A hierarchy-first method reproduces the failure, finds the first divergence, and narrows by level before any code changes.

    Debug flow from reproduction through first divergence and hierarchy narrowing to a proven root cause.
    The four debug steps in order. Each step narrows the search before waveforms are opened.

    Lessons in this topic

    4 lessons, about 13 min

    1. 1Debug hierarchy before touching codeYou can reproduce a failure from its seed, narrow it through three levels, and put the wave cursor on the first divergence.3 min
    2. 2Controlled dumps and trigger captureYou can gate dumps behind a plusarg, arm a trigger on a violation, and explain why a window needs a replay.3 min
    3. 3Waveform bug patterns: latch and raceYou can recognise a stale combinational latch and a blocking-assignment collapse in a waveform, and prove each with a varied input history.4 min
    4. 4Handshake protocol violationYou can state the valid/ready stability rule, write both assertions, and build a monitor that counts violations.3 min
    Check yourself A test fails once in long random runs with no wave dumped. What is the first step?

    Reproduce it with the logged seed and plusargs, then arm a trigger on the failure signature. Dumping everything from the start slows the run and buries the event.

    Interview

    “Walk through a failure that was debugged.” A strong answer names the levels: the top-level symptom, the contract that broke, and the local root cause, with the wave or check that proved each step.

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Debug hierarchy before touching code

    • Log the seed, plusargs and first failing transaction before opening any wave; the same seed must fail at the same cycle.

    • Drop a level only when the level above has named a suspect.

    • The cursor belongs on the first divergence, not the last.

    Controlled dumps and trigger capture

    • Dumps are off by default; +WAVE_ON turns them on for the failing seed without recompiling.

    • A trigger prints a snapshot and finishes conditionally, never a bare $stop.

    • $dumpon cannot recover the past: reproduce the failure cycle, then rerun with a window that starts before it.

    Waveform bug patterns: latch and race

    • A combinational block with no idle assignment holds its old value, and the wave shows a stale grant.

    • With blocking assignments in one process, both registers sample din at the edge, so the second stage adds no delay.

    • Equal outputs prove nothing: repeated inputs also make correct stages equal.

    Handshake protocol violation

    • A transfer happens when valid and ready are both high; the source owns valid and the payload, the sink owns ready.

    • Valid stays asserted until the handshake, and the payload stays stable while valid waits for ready.

    • Both assertions are needed: one for valid, one for data.

    Rule of thumb: once offered, a payload cannot change until the handshake.

    Practise it

    • Mini project: the capstone: a resilient streaming peripheral, stage by stage

    • Practice question: Waveform debug: write transaction timeout

    • Practice question: FSM incomplete case and unique0: simulation versus synthesis

    • Practice question: Two-stage valid/ready pipeline with backpressure

    • Code lab: AXI stream handshake

    • Interview: run a mock interview on this topic

    PreviousNext: Debug hierarchy before touching code

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    See also

    • Low-Power RTL Hub
    • DFT and Scan Hub
    • Physical Awareness Hub