DFT-Ready RTL · RTL Design

Part 9 · Senior · Senior

3topics
3lessons

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The DFT team owns insertion and ATPG methodology; the RTL owner makes the design controllable, observable, and safe in test mode. This topic defines that boundary and links detailed DFT mechanisms to the dedicated course.

A dual-clock sensor peripheral is the worked integration. It contains gated functional clocks, asynchronous resets, two SRAMs, external pins, and one analog-status input that can become unknown. Each lesson prepares that same block for scan, memory test, boundary access, and compressed response capture.

Block diagram: AON test control drives the sample-domain registers, the bus-domain registers and the pin mux. analog_status enters the sample registers through a test clamp. The sample SRAM 256x16 with its MBIST sits in the sample domain and the config SRAM 64x32 with its MBIST in the bus domain. The TAP reaches both memories.

The sensor peripheral used through this topic: two clock domains under one always-on test controller, one SRAM with its own MBIST per domain, a TAP for memory and pin access, and an analog input clamped in test.

Read the diagram top down: who owns clocks and resets (AON), what they control (the two register domains and pins), and what reaches the memories (the TAP).

The instance names and mode artifacts below define the integration contract. AON test control remains powered throughout test; authorized lifecycle entry is an external prerequisite.

Lessons in this topic

3 lessons, about 12 min

Scan-Ready CodingYou can spot RTL features that block scan, replace them with approved patterns, and centralise test controls.4 min
Test Clocks, Resets, and ModesYou can plan entry and exit sequences for test mode, set a reset policy for shift and capture, and say where lockup latches belong.5 min
Memory, JTAG, Compression, and HandoffYou can write the DFT handoff for memories, JTAG and compression, and list what must be true before it is accepted.3 min

Check yourself Should an RTL team hand-code scan chains for ordinary functional flops?

Usually no. Synthesis/DFT tools replace and stitch scan cells. RTL supplies scan-friendly clocks, resets, test modes, memories, and controllability/observability.

Revision sheet

The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

Scan-Ready Coding

Shifting needs controllable repeated pulses; bypass a functional divider with an approved clock wrapper.
Give test control explicit reset ownership, and clamp analog status only in authorised test mode.
Run DFT lint early, and list every non-scan register with the reason it is safe.

Test Clocks, Resets, and Modes

Take ownership of clocks and resets only with clocks stopped and reset asserted, then release resets with legal test clocks.
Asynchronous clock domains get separate chains; lockup latches serve related domains and opposite edges.
Entry and exit acknowledgements need bounded watchdogs and a safe parked error state.

Memory, JTAG, Compression, and Handoff

Map every memory instance exactly once to MBIST and repair policy, and version the instance list.
Find X sources before compression insertion; analog clamp = 0 needs a separate analog test plan.
MBIST completion does not allow functional traffic until reset, configuration and domain readiness finish.

Practise it

Mini project: the capstone: a resilient streaming peripheral, stage by stage
Code lab: Scan chain stub
Code lab: JTAG tap model
Interview: run a mock interview on this topic

Up nextScan-Ready Coding

Practice this lesson Report an error

Lessons in this topic

3 lessons, about 12 min

Scan-Ready CodingYou can spot RTL features that block scan, replace them with approved patterns, and centralise test controls.4 min
Test Clocks, Resets, and ModesYou can plan entry and exit sequences for test mode, set a reset policy for shift and capture, and say where lockup latches belong.5 min
Memory, JTAG, Compression, and HandoffYou can write the DFT handoff for memories, JTAG and compression, and list what must be true before it is accepted.3 min

Check yourself Should an RTL team hand-code scan chains for ordinary functional flops?

Usually no. Synthesis/DFT tools replace and stitch scan cells. RTL supplies scan-friendly clocks, resets, test modes, memories, and controllability/observability.

Revision sheet

The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

Scan-Ready Coding

Shifting needs controllable repeated pulses; bypass a functional divider with an approved clock wrapper.

Give test control explicit reset ownership, and clamp analog status only in authorised test mode.

Run DFT lint early, and list every non-scan register with the reason it is safe.

Test Clocks, Resets, and Modes

Take ownership of clocks and resets only with clocks stopped and reset asserted, then release resets with legal test clocks.

Asynchronous clock domains get separate chains; lockup latches serve related domains and opposite edges.

Entry and exit acknowledgements need bounded watchdogs and a safe parked error state.

Memory, JTAG, Compression, and Handoff

Map every memory instance exactly once to MBIST and repair policy, and version the instance list.

Find X sources before compression insertion; analog clamp = 0 needs a separate analog test plan.

MBIST completion does not allow functional traffic until reset, configuration and domain readiness finish.