Scan test walks the design through a fixed order of modes: load the chains, capture one functional response, unload it while loading the next pattern, and finally exit. Each mode needs its own clock and reset policy.
The peripheral's two clock domains become separate scan domains. The test clock controller supplies slow shift pulses and controlled at-speed capture, while lockup latches handle chain crossings selected by the DFT stitching flow.
Each slot shows the values just after one test-clock edge; chain is the three cells as one number, cell 2 first.
Slots 0 to 3 (shift): se is 1 and si supplies 1, 0, 1, so the chain fills to 101 one cell per pulse.
Slot 3: se falls before the next edge. It must settle with setup margin, because the next pulse is the capture.
Slot 4 (capture): the chain takes the functional value d = 011 in one pulse.
Slots 4 to 6 (unload): so shows 0, 1, 1: the captured word leaves, cell 2 first, while new si bits enter behind it.
Shift moves data cell to cell with almost no logic between them, so it stresses minimum delay (hold). Capture runs the functional paths, so at-speed capture stresses maximum delay (setup).
Mode | sample / bus clocks; scan_enable | Reset, clamp and memory policy | Dominant risk |
|---|---|---|---|
Functional | Independent PLL / bus clocks; 0 | Functional reset owners; analog clamp off; functional SRAM owners | Test controls must stay inactive and nonintrusive |
Shift | Many low-frequency ATE pulses through both approved wrappers; 1 | Test resets inactive and stable; ICG shift overrides on; analog clamp on; SRAM read outputs masked | Hold, chain crossing, lockup-latch placement |
Stuck-at capture | One controlled sample pulse, then one bus pulse; 0 | Resets inactive; clamp on; cross-domain capture inputs held by reviewed test constraints | Functional-mode setup and reset constraints |
At-speed capture | Selected domain's OCC supplies a launch/capture pair at functional rate; other domain parked; 0 | Resets inactive; clamp on; no uncontrolled asynchronous launch/capture relationship | PLL/OCC sequence and setup timing |
Two more modes use the same peripheral without scan shifting:
MBIST: the selected macro's approved test clock runs with scan shifting off. The wrapper owns the selected SRAM exclusively, functional clients are parked, and the macro's own initialization and latency protocol applies.
Boundary access: TCK drives the TAP while functional and OCC clocks are parked. The pin safe-state mux is owned by TAP/AON, and resets and output enables are held per pin policy.
The numbers match the states in the diagram above.
Enter (1 to 2): authorize test; stop new traffic and drain or explicitly cancel pending work; park external output enables and clamp the analog input before observing scan responses. Stop functional clocks through acknowledged glitchless wrappers, assert domain resets, transfer clock/reset ownership to AON test control, and program stable mode controls while clocks are stopped.
Shift (2): supply legal test clocks to release domain resets synchronously, then hold resets inactive. Assert scan_enable and ICG shift overrides before the first shift edge; load each separate chain completely.
Capture (3): stop shift pulses low, deassert scan_enable with required setup, configure the selected OCC and capture clamps, then issue only the approved pulse sequence.
Shift again (4): return to shift while clocks are stopped and controls settle; unload the response while loading the next pattern.
Exit (5 to 1): stop test pulses low, assert domain resets to discard scan/MBIST state, restore functional clock/reset and SRAM ownership through acknowledged wrappers, restart clocks and initialize state. Release resets synchronously; release clamps/pin parking only after domain readiness, then resume traffic.
Lockup latches absorb phase and skew risk where a scan chain crosses between related, synchronous clock domains or between opposite clock edges; asynchronous domains get separate chains, as above. DFT tools usually insert them, but RTL and clock architecture must expose correct domain relationships.
Shift moves data through adjacent scan cells with little combinational delay, stressing minimum delay. Capture exercises functional paths at speed, stressing maximum delay.
That edge would shift again instead of capturing, so the functional value 011 would never enter the chain and the unload would show shifted pattern bits instead of the response.