Shift vs Capture Timing turns DFT intent into measurable release confidence. Shift mode is hold-sensitive while capture mode is setup-sensitive; closure must preserve both under test clocking assumptions. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.
When shift hold violations, capture setup failures, at-speed pattern pass rate moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?
DFT CLOSURE FLOW - Shift vs Capture Timing
scan/test architecture
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v
ATPG constraints + fault models
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v
pattern generation + compression
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v
timing/power/physical validation
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v
silicon diagnosis and release signoff
Debug rule: always state metric, run tags, and owning team with any claim.Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.
shift mode: hold-dominant
capture mode: setup-dominant
Do not sign off one without the other.DFT FLOW - Shift vs Capture Timing
scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
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controllability shift balance channel use coverage silicon correlation
Primary metric: shift hold violations, capture setup failures, at-speed pattern pass rateDFT OWNERSHIP LAYERS - Shift vs Capture Timing
layer owns failure mode
---------------- -------------------------- -------------------------
rtl/architecture scanability hooks uncontrollable logic
atpg/constraints legal pattern intent aborts, low coverage
physical/clocking chain route + test clocks shift hold/timing escapes
tester/program pattern apply integrity false binning / bad fails
quality signoff release criteria escapes or schedule slipPrimary metric: shift hold violations, capture setup failures, at-speed pattern pass rate.
Primary artifact: shift/capture timing report, at-speed validation logs, path-group summary.
Owners to bring into review: STA owner, DFT owner, PD owner.
One failing signature and one reduced reproduction path.
Exact run tags for constraints, patterns, and tester program.
OWNERSHIP MAP - Shift vs Capture Timing
artifact owner
---------------- -----------------
architecture/report STA owner
constraints/setup DFT owner
physical/test PD owner
Name an owner for each failing metric cluster.Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.
State metric and run tags with every claim.
Connect every fix to a regression matrix.
Treat quality, timing, and power as coupled.
Coverage-centric decisions without legality checks.
Pattern changes without tester correlation.
Release calls without owner signoff.
Test signoff fails when shift/capture timing and test power are treated independently.
TEST SIGNOFF LOOP
test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> releaseTEST CURRENT
functional current baseline
scan shift current peak-risk zonetest-mode STA report
shift/capture split
test power IR map
waiver tracker
At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.
Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.