DFT Physical Integration

Section goal

Physical implications of scan, compression, and BIST logic on floorplan, routing, and handoff.

How to study this section

1. Start with the topic hub for architecture and ownership context.

2. Use mechanism and reports pages to map assumptions to metrics.

3. Use debug and worked examples for real closure patterns.

4. Finish with checklist and silicon impact before release decisions.

Topics

1. scan-chain-physical-effects/ - Scan Chain Physical Effects

2. test-logic-floorplan/ - Test Logic Floorplan

3. dft-pd-handoff/ - DFT-PD Handoff

4. physical-dft-debug/ - Physical DFT Debug

Related topics

• DFT course hub

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?