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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
    • Scan Chain Physical Effects
    • Test Logic Floorplan
    • DFT-PD Handoff
    • Physical DFT Debug
      • Physical DFT Debug: Mechanism
      • Physical DFT Debug: Inputs & Outputs
      • Physical DFT Debug: Reports & Metrics
      • Physical DFT Debug: Debug Playbook
      • Physical DFT Debug: Worked Example
      • Physical DFT Debug: Pitfalls & Red Flags
      • Physical DFT Debug: Interview Drills
      • Physical DFT Debug: Review Checklist
      • Physical DFT Debug: Theory Deep Dive
      • Physical DFT Debug: Design Space
      • Physical DFT Debug: Expanded Case Study
      • Physical DFT Debug: Step-by-Step Walkthrough
      • Physical DFT Debug: Comparison Matrix
      • Physical DFT Debug: Software / Programmer View
      • Physical DFT Debug: Silicon PPA Impact
    • DFT Physical Integration: Tricky Q&A
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Physical DFT Debug
  1. Topics
  2. Design for Test
  3. DFT Physical Integration
  4. Physical DFT Debug
  5. Physical DFT Debug: Review Checklist

DFT / ATPG · All levels

Physical DFT Debug: Review Checklist

Review Checklist for Physical DFT Debug.

On this page

    Review checklist

    Review Checklist for Physical DFT Debug focuses on physical root-cause turnaround, repeat DFT route violations, signoff escape risk. The goal is to convert metric movement into mechanism, owner, and release decision.

    • Run tags and scenario context are explicit.

    • Constraints and legality assumptions are documented.

    • Quality, timing, and test-power checks are included.

    • Diagnosis evidence supports residual-risk decision.

    • Owners signed: PD owner, STA owner, DFT owner.

    Signoff ownership

    Diagram
    OWNERSHIP MAP - Physical DFT Debug
    
    artifact              owner
    ----------------      -----------------
    architecture/report PD owner
    constraints/setup   STA owner
    physical/test       DFT owner
    
    Name an owner for each failing metric cluster.

    DFT deep dive

    Physical integration quality decides whether DFT architecture survives implementation realities.

    Concept diagram

    Diagram
    PHYSICAL DFT FLOW
    
    chain planning -> floorplan placement -> route -> test timing/power validation

    Metric graph

    Diagram
    ROUTING BURDEN
    
    poor chain order -> longer routes -> more hold buffers

    Reports and artifacts

    • scan physical wirelength

    • congestion heatmap

    • test clock skew

    • handoff issue tracker

    Mini case study

    Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

    Debug branches

    • Correlate chain order with congestion

    • Place compression logic near chain clusters

    • Keep DFT-PD handoff versioned

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Physical DFT debug traces violations to chain ordering, buffering strategy, clock topology, or extraction/view mismatches.

    Metric: physical root-cause turnaround, repeat DFT route violations, signoff escape risk

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    See also

    • Physical DFT Debug: Mechanism
    • Physical DFT Debug: Inputs & Outputs
    • Physical DFT Debug: Reports & Metrics