Scan Fundamentals

Section goal

Mux-DFF scan architecture, chain stitching rules, shift/capture clocks, and scan-ready RTL conventions.

How to study this section

1. Start with the topic hub for architecture and ownership context.

2. Use mechanism and reports pages to map assumptions to metrics.

3. Use debug and worked examples for real closure patterns.

4. Finish with checklist and silicon impact before release decisions.

Topics

1. scan-cell-architecture/ - Scan Cell Architecture

2. chain-stitching-rules/ - Chain Stitching Rules

3. clocking-for-test/ - Clocking for Test

4. scan-ready-rtl/ - Scan-Ready RTL

Related topics

• DFT course hub

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?