Mux-DFF scan architecture, chain stitching rules, shift/capture clocks, and scan-ready RTL conventions.
Start with the topic hub for architecture and ownership context.
Use mechanism and reports pages to map assumptions to metrics.
Use debug and worked examples for real closure patterns.
Finish with checklist and silicon impact before release decisions.
scan-cell-architecture/ - Scan Cell Architecture
chain-stitching-rules/ - Chain Stitching Rules
clocking-for-test/ - Clocking for Test
scan-ready-rtl/ - Scan-Ready RTL
Scan architecture quality determines whether ATPG can control and observe real silicon state.
SCAN INSERTION FLOW
scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoffCHAIN BALANCE
chain length spread
low spread = better shift time
high spread = routing + hold riskscan insertion summary
chain balance report
scan DRC log
clocking legality report
Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.
Check scan replacement first
Audit chain legality by domain
Validate shift/capture clocks
Ask: what evidence proves this DFT decision is safe for production?