Chain Stitching Rules turns DFT intent into measurable release confidence. Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.
When chain balance spread, max chain length, scan shift time moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?
DFT CLOSURE FLOW - Chain Stitching Rules
scan/test architecture
|
v
ATPG constraints + fault models
|
v
pattern generation + compression
|
v
timing/power/physical validation
|
v
silicon diagnosis and release signoff
Debug rule: always state metric, run tags, and owning team with any claim.Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.
SCAN CHAINS
clock_domain_A: FF1 -> FF2 -> FF3 -> SO
clock_domain_B: FF4 -> FF5 -> FF6 -> SO
Rules:
1) keep domains legal
2) balance chain length
3) avoid long physical detoursDFT FLOW - Chain Stitching Rules
scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
| | | | |
controllability shift balance channel use coverage silicon correlation
Primary metric: chain balance spread, max chain length, scan shift timeDFT OWNERSHIP LAYERS - Chain Stitching Rules
layer owns failure mode
---------------- -------------------------- -------------------------
rtl/architecture scanability hooks uncontrollable logic
atpg/constraints legal pattern intent aborts, low coverage
physical/clocking chain route + test clocks shift hold/timing escapes
tester/program pattern apply integrity false binning / bad fails
quality signoff release criteria escapes or schedule slipPrimary metric: chain balance spread, max chain length, scan shift time.
Primary artifact: chain map, balance histogram, stitch rule deck.
Owners to bring into review: DFT owner, PD owner, implementation owner.
One failing signature and one reduced reproduction path.
Exact run tags for constraints, patterns, and tester program.
OWNERSHIP MAP - Chain Stitching Rules
artifact owner
---------------- -----------------
architecture/report DFT owner
constraints/setup PD owner
physical/test implementation owner
Name an owner for each failing metric cluster.Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.
State metric and run tags with every claim.
Connect every fix to a regression matrix.
Treat quality, timing, and power as coupled.
Coverage-centric decisions without legality checks.
Pattern changes without tester correlation.
Release calls without owner signoff.
Scan architecture quality determines whether ATPG can control and observe real silicon state.
SCAN INSERTION FLOW
scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoffCHAIN BALANCE
chain length spread
low spread = better shift time
high spread = routing + hold riskscan insertion summary
chain balance report
scan DRC log
clocking legality report
Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.
Check scan replacement first
Audit chain legality by domain
Validate shift/capture clocks
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.