Chain Stitching Rules: Theory Deep Dive

Foundational theory

Chain Stitching Rules is central to Scan Fundamentals. Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain.

• Primary metric: chain balance spread, max chain length, scan shift time

• Primary artifact: chain map, balance histogram, stitch rule deck

• Owners: DFT owner, PD owner, implementation owner

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Chain Stitching Rules issues can create coverage escapes, unstable production bins, or long debug loops. Scan architecture determines controllability and observability quality.

Mental model

CHAIN STITCHING (example)
clock/power legal groups -> balanced chains -> routed scan order

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open chain balance spread, max chain length, scan shift time trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect chain map, balance histogram, stitch rule deck and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Chain stitching constraints

SCAN CHAINS

clock_domain_A: FF1 -> FF2 -> FF3 -> SO
clock_domain_B: FF4 -> FF5 -> FF6 -> SO

Rules:
1) keep domains legal
2) balance chain length
3) avoid long physical detours

Layer responsibilities

DFT OWNERSHIP LAYERS - Chain Stitching Rules

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

Scan architecture determines controllability and observability quality.