DenseChip

DFT / ATPG · All levels

Chain Stitching Rules: Comparison Matrix

Comparison Matrix for Chain Stitching Rules.

Comparison matrix

Scan decisions trade shift time, routing burden, and debug clarity.

diagram
+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | safe           | higher cost    | ramp-sensitive |
| Balanced         | practical      | needs rigor    | production     |
| Aggressive       | fast           | escape risk    | schedule pressure |
| Architecture     | durable        | slow           | repeated pain  |
+------------------+----------------+----------------+----------------+

When to choose each approach

  • Tie approach to product risk and tester constraints

Interview traps

  • Optimizing one metric only

  • No regression ownership

Evidence comparison

diagram
DFT EVIDENCE MATRIX - Chain Stitching Rules

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report    | fault detect trends    | silicon root cause       | inspect bucket details  |
| pattern diff       | generation changes     | architecture quality     | replay suspect patterns |
| timing/power report| test closure margin    | diagnosis confidence     | correlate fail logs     |
| diagnosis summary  | likely defect classes  | ownership decision       | assign action owner     |
| signoff checklist  | process completeness   | correctness of evidence  | peer review artifacts   |
+-------------------+------------------------+--------------------------+-------------------------+

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

diagram
SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

diagram
CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

  • scan insertion summary

  • chain balance report

  • scan DRC log

  • clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

  • Check scan replacement first

  • Audit chain legality by domain

  • Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

  • State metric, lot/corner context, and pattern tag with every claim.

  • Treat timing, power, and quality as one signoff problem.

Common pitfalls

  • Chasing coverage without legality checks.

  • Ignoring test-power side effects of pattern changes.

  • Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain.

Metric: chain balance spread, max chain length, scan shift time

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