DFT / ATPG · All levels

Chain Stitching Rules: Review Checklist

Review Checklist for Chain Stitching Rules.

Review checklist

Review Checklist for Chain Stitching Rules focuses on chain balance spread, max chain length, scan shift time. The goal is to convert metric movement into mechanism, owner, and release decision.

  • Run tags and scenario context are explicit.

  • Constraints and legality assumptions are documented.

  • Quality, timing, and test-power checks are included.

  • Diagnosis evidence supports residual-risk decision.

  • Owners signed: DFT owner, PD owner, implementation owner.

Signoff ownership

diagram
OWNERSHIP MAP - Chain Stitching Rules

artifact              owner
----------------      -----------------
architecture/report DFT owner
constraints/setup   PD owner
physical/test       implementation owner

Name an owner for each failing metric cluster.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

diagram
SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

diagram
CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

  • scan insertion summary

  • chain balance report

  • scan DRC log

  • clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

  • Check scan replacement first

  • Audit chain legality by domain

  • Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

  • State metric, lot/corner context, and pattern tag with every claim.

  • Treat timing, power, and quality as one signoff problem.

Common pitfalls

  • Chasing coverage without legality checks.

  • Ignoring test-power side effects of pattern changes.

  • Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain.

Metric: chain balance spread, max chain length, scan shift time