Worked example

Worked Example for Chain Stitching Rules focuses on chain balance spread, max chain length, scan shift time. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on chain balance spread, max chain length, scan shift time. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Chain Stitching Rules

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: chain balance spread, max chain length, scan shift time

Chain stitching constraints

SCAN CHAINS

clock_domain_A: FF1 -> FF2 -> FF3 -> SO
clock_domain_B: FF4 -> FF5 -> FF6 -> SO

Rules:
1) keep domains legal
2) balance chain length
3) avoid long physical detours

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against chain map, balance histogram, stitch rule deck.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Chain Stitching Rules

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan flops are stitched into chains based on clock, power, and physical constraints; poor stitching increases test time and routing pain.

Metric: chain balance spread, max chain length, scan shift time