IEEE 1149.1 TAP design, board-level test access, and package interface constraints.
Start with the topic hub for architecture and ownership context.
Use mechanism and reports pages to map assumptions to metrics.
Use debug and worked examples for real closure patterns.
Finish with checklist and silicon impact before release decisions.
jtag-tap-architecture/ - JTAG TAP Architecture
boundary-scan-cells/ - Boundary Scan Cells
debug-access-port/ - Debug Access Port
package-test-interface/ - Package Test Interface
Boundary scan and JTAG are board-level contracts, not just RTL features.
JTAG ACCESS
TAP controller -> instruction register -> boundary/data register -> board test/debugBOARD TEST READINESS
instruction coverage vs pin controllabilityTAP compliance report
boundary cell coverage matrix
EXTEST/INTEST results
debug lock policy log
Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.
Verify TAP state transitions
Audit package pin ownership
Check security lifecycle lock behavior
Ask: what evidence proves this DFT decision is safe for production?