Boundary Scan & JTAG

Section goal

IEEE 1149.1 TAP design, board-level test access, and package interface constraints.

How to study this section

1. Start with the topic hub for architecture and ownership context.

2. Use mechanism and reports pages to map assumptions to metrics.

3. Use debug and worked examples for real closure patterns.

4. Finish with checklist and silicon impact before release decisions.

Topics

1. jtag-tap-architecture/ - JTAG TAP Architecture

2. boundary-scan-cells/ - Boundary Scan Cells

3. debug-access-port/ - Debug Access Port

4. package-test-interface/ - Package Test Interface

Related topics

• DFT course hub

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?