Use these drills after completing all topics in Boundary Scan & JTAG. Answer with metric, mechanism, evidence, owner, and regression plan.
[INT][DFT][BOUNDARY-SCAN-JTAG]
Q: Why is JTAG a security topic too?
A:
Debug access can expose privileged controls; lifecycle lock policy must be validated in all states.
FOLLOW-UP TRAP: Verifying only board-test use cases.[INT][DFT][BOUNDARY-SCAN-JTAG]
Q: What breaks boundary scan most often at system level?
A:
Pinmux/lifecycle interactions and package ownership mismatches between RTL and board assumptions.
FOLLOW-UP TRAP: Debugging TAP only and ignoring package contracts.METRIC -> MECHANISM -> EVIDENCE -> FIX -> REGRESSIONJTAG ACCESS
TAP controller -> instruction register -> boundary/data register -> board test/debugState metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.