Test-mode constraints, shift/capture timing closure, and test power/IR management.
Start with the topic hub for architecture and ownership context.
Use mechanism and reports pages to map assumptions to metrics.
Use debug and worked examples for real closure patterns.
Finish with checklist and silicon impact before release decisions.
test-mode-sdc/ - Test-Mode SDC
shift-capture-timing/ - Shift vs Capture Timing
test-power-ir/ - Test Power & IR
test-signoff-reports/ - Test Signoff Reports
Test signoff fails when shift/capture timing and test power are treated independently.
TEST SIGNOFF LOOP
test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> releaseTEST CURRENT
functional current baseline
scan shift current peak-risk zonetest-mode STA report
shift/capture split
test power IR map
waiver tracker
At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.
Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots
Ask: what evidence proves this DFT decision is safe for production?