Test Timing & Power

Section goal

Test-mode constraints, shift/capture timing closure, and test power/IR management.

How to study this section

1. Start with the topic hub for architecture and ownership context.

2. Use mechanism and reports pages to map assumptions to metrics.

3. Use debug and worked examples for real closure patterns.

4. Finish with checklist and silicon impact before release decisions.

Topics

1. test-mode-sdc/ - Test-Mode SDC

2. shift-capture-timing/ - Shift vs Capture Timing

3. test-power-ir/ - Test Power & IR

4. test-signoff-reports/ - Test Signoff Reports

Related topics

• DFT course hub

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?