DFT / ATPG · All levels

Test Power & IR

Test Timing & Power: Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.

What this topic teaches

Test Power & IR turns DFT intent into measurable release confidence. Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When peak test-mode current, IR drop hotspots, scan-induced thermal spikes moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

diagram

DFT CLOSURE FLOW - Test Power & IR

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Scan power stress

diagram

scan toggling burst -> peak current -> IR droop / thermal rise

Mitigation: power-aware ATPG + pattern scheduling + capture staggering

Process sequence

diagram

DFT FLOW - Test Power & IR

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes

Ownership layers

diagram

DFT OWNERSHIP LAYERS - Test Power & IR

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

Primary metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes.
Primary artifact: test power report, IR map, power-aware ATPG settings log.
Owners to bring into review: power signoff owner, ATPG owner, DFT lead.
One failing signature and one reduced reproduction path.
Exact run tags for constraints, patterns, and tester program.

Ownership map

diagram

OWNERSHIP MAP - Test Power & IR

artifact              owner
----------------      -----------------
architecture/report power signoff owner
constraints/setup   ATPG owner
physical/test       DFT lead

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

State metric and run tags with every claim.
Connect every fix to a regression matrix.
Treat quality, timing, and power as coupled.

Common pitfalls

Coverage-centric decisions without legality checks.
Pattern changes without tester correlation.
Release calls without owner signoff.

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

diagram

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

test-mode STA report
shift/capture split
test power IR map
waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.

Common pitfalls

Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.

Practice this lesson