Test Power & IR: Interview Drills

Interview drills

Interview Drills for Test Power & IR focuses on peak test-mode current, IR drop hotspots, scan-induced thermal spikes. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe peak test-mode current, IR drop hotspots, scan-induced thermal spikes on Test Power & IR. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.
3. Requests test power report, IR map, power-aware ATPG settings log.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Scan power stress

scan toggling burst -> peak current -> IR droop / thermal rise

Mitigation: power-aware ATPG + pattern scheduling + capture staggering

Root-cause narrative

ROOT-CAUSE TREE - Test Power & IR

peak test-mode current, IR drop hotspots, scan-induced thermal spikes regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.

Metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes