Shift speed, capture strategy, and pattern scheduling trade risk and throughput.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Conservative | safe | higher cost | ramp-sensitive |
| Balanced | practical | needs rigor | production |
| Aggressive | fast | escape risk | schedule pressure |
| Architecture | durable | slow | repeated pain |
+------------------+----------------+----------------+----------------+Tie approach to product risk and tester constraints
Optimizing one metric only
No regression ownership
DFT EVIDENCE MATRIX - Test Power & IR
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report | fault detect trends | silicon root cause | inspect bucket details |
| pattern diff | generation changes | architecture quality | replay suspect patterns |
| timing/power report| test closure margin | diagnosis confidence | correlate fail logs |
| diagnosis summary | likely defect classes | ownership decision | assign action owner |
| signoff checklist | process completeness | correctness of evidence | peer review artifacts |
+-------------------+------------------------+--------------------------+-------------------------+Test signoff fails when shift/capture timing and test power are treated independently.
TEST SIGNOFF LOOP
test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> releaseTEST CURRENT
functional current baseline
scan shift current peak-risk zonetest-mode STA report
shift/capture split
test power IR map
waiver tracker
At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.
Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.
Metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes
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