Step-by-step analysis walkthrough

Use when you own Test Power & IR in a DFT closure review.

1. Open release criteria and failing metric dashboard.

2. Partition failures by pattern family and operating context.

3. Inspect constraints, clocks, masks, and unknown handling.

4. Check architecture assumptions against implementation reality.

5. Review diagnosis evidence for repeatability.

6. Assign owner and propose smallest high-confidence change.

7. Run timing, power, and quality regressions.

8. Capture final signoff or waiver decision.

Artifacts to collect

• test power report, IR map, power-aware ATPG settings log

• pattern tag manifest

• tester program revision

• signoff checklist

• owner tracker

Decision memo template

DFT DECISION MEMO - Test Power & IR
scenario:
metric:
hypothesis:
fix:
regression:
owners: power signoff owner, ATPG owner, DFT lead

Reference visuals

Scan power stress

scan toggling burst -> peak current -> IR droop / thermal rise

Mitigation: power-aware ATPG + pattern scheduling + capture staggering

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.

Metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes