Review Checklist for Test Power & IR focuses on peak test-mode current, IR drop hotspots, scan-induced thermal spikes. The goal is to convert metric movement into mechanism, owner, and release decision.
Run tags and scenario context are explicit.
Constraints and legality assumptions are documented.
Quality, timing, and test-power checks are included.
Diagnosis evidence supports residual-risk decision.
Owners signed: power signoff owner, ATPG owner, DFT lead.
OWNERSHIP MAP - Test Power & IR
artifact owner
---------------- -----------------
architecture/report power signoff owner
constraints/setup ATPG owner
physical/test DFT lead
Name an owner for each failing metric cluster.Test signoff fails when shift/capture timing and test power are treated independently.
TEST SIGNOFF LOOP
test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> releaseTEST CURRENT
functional current baseline
scan shift current peak-risk zonetest-mode STA report
shift/capture split
test power IR map
waiver tracker
At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.
Tag test and functional corners separately
Check hold in shift mode
Correlate fail bins with power hotspots
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.
Metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes
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