Foundational theory

Test Power & IR is central to Test Timing & Power. Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• Scan activity can exceed functional switching, so pattern scheduling and power-aware ATPG are needed to avoid IR and thermal escapes.

• Primary metric: peak test-mode current, IR drop hotspots, scan-induced thermal spikes

• Primary artifact: test power report, IR map, power-aware ATPG settings log

• Owners: power signoff owner, ATPG owner, DFT lead

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Test Power & IR issues can create coverage escapes, unstable production bins, or long debug loops. Test timing and power closure are coupled and must be signed together.

Mental model

scan toggling burst -> peak current -> IR droop / thermal rise

Mitigation: power-aware ATPG + pattern scheduling + capture staggering

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open peak test-mode current, IR drop hotspots, scan-induced thermal spikes trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect test power report, IR map, power-aware ATPG settings log and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Scan power stress

scan toggling burst -> peak current -> IR droop / thermal rise

Mitigation: power-aware ATPG + pattern scheduling + capture staggering

Layer responsibilities

DFT OWNERSHIP LAYERS - Test Power & IR

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

Test timing and power closure are coupled and must be signed together.