DFT / ATPG - Scan, Compression, and Silicon Test

Course promise

This is the production DFT course for silicon teams. It teaches how to architect scan and test flows, close quality metrics, and debug silicon mismatches with strong release discipline.

• Scan, compression, ATPG, MBIST/LBIST, and JTAG foundations.

• Test timing, power, and physical integration closure.

• Diagnosis and yield learning loops.

• Every topic follows metric -> mechanism -> evidence -> owner -> regression -> decision.

Course map

scan fundamentals
  -> compression and diagnosis
  -> ATPG and coverage closure
  -> MBIST/LBIST and JTAG
  -> test timing/power + physical integration
  -> interview and release readiness

Related topics

• Physical Design - integration

• Silicon bring-up course

• RTL - DFT scan module

Section deep dive

DFT signoff needs traceable architecture, constraints, and silicon evidence.

Concept diagram

scan architecture -> pattern generation -> silicon evidence

Metric graph

coverage and quality trend

Reports and artifacts

• coverage

• pattern count

• test timing

• diagnosis

Mini case study

Tag every run and artifact to avoid ghost regressions.

Debug branches

• Check constraints first

Senior review question

Ask: what evidence proves this DFT decision is safe for production?