Boundary Scan Cells: Interview Drills

Interview drills

Interview Drills for Boundary Scan Cells focuses on boundary cell insertion coverage, pin-level controllability, EXTEST pass rate. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe boundary cell insertion coverage, pin-level controllability, EXTEST pass rate on Boundary Scan Cells. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.
3. Requests boundary cell map, EXTEST report, pin coverage matrix.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Boundary cell at IO

core logic <-> boundary cell <-> package pin

EXTEST drives/observes board interconnect independent of core paths.

Root-cause narrative

ROOT-CAUSE TREE - Boundary Scan Cells

boundary cell insertion coverage, pin-level controllability, EXTEST pass rate regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate