Boundary Scan Cells: Expanded Case Study

Extended case study

Release review: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate regresses after a test-flow update touching Boundary Scan Cells.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• boundary cell insertion coverage, pin-level controllability, EXTEST pass rate regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Boundary Scan Cells: Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Fix and validation

• Apply bounded fix with owner

• Re-run boundary cell map, EXTEST report, pin coverage matrix

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Boundary Scan Cells
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Boundary Scan Cells

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate