Boundary Scan Cells: Worked Example

Worked example

Worked Example for Boundary Scan Cells focuses on boundary cell insertion coverage, pin-level controllability, EXTEST pass rate. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on boundary cell insertion coverage, pin-level controllability, EXTEST pass rate. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Boundary Scan Cells

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate

Boundary cell at IO

core logic <-> boundary cell <-> package pin

EXTEST drives/observes board interconnect independent of core paths.

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against boundary cell map, EXTEST report, pin coverage matrix.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Boundary Scan Cells

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate