RTL / integration view

Pinmux and lifecycle logic must preserve legal JTAG paths.

What teams feel

• Unexpected untestables

• clock/reset test-mode conflicts

RTL structure impact

• Scan hooks

• mode controls

• debug access gating

Tool interaction

• Synthesis transforms affecting scan paths

• clock-gating interaction

Mitigations

• DFT lint gates

• test-aware coding standards

• joint RTL/DFT reviews

RTL VIEW - Boundary Scan Cells
// mode logic changed -> recheck controllability and constraints

Layer touch points

DFT OWNERSHIP LAYERS - Boundary Scan Cells

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate