Design space exploration

For Boundary Scan Cells, release options trade quality, tester cost, and schedule risk.

Option A - conservative

• Conservative quality: helps debug confidence

• Risk: higher test cost

• Validate with: first production ramps

Option B - balanced

• Balanced release: helps quality and cost

• Risk: needs discipline

• Validate with: mainstream products

Option C - aggressive

• Aggressive schedule: helps faster closure

• Risk: escape risk

• Validate with: late tapeout pressure

Option D - architecture change

• Architecture change: helps long-term quality

• Risk: schedule hit

• Validate with: chronic recurring failures

DESIGN SPACE - Boundary Scan Cells
quality <-> tester cost <-> schedule

Design pitfalls

• No ownership for quality gap

• Fixing one metric while regressing another

Tradeoff curve

BEFORE / AFTER - Boundary Scan Cells

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.

Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate