DFT / ATPG · All levels
Boundary Scan Cells: Comparison Matrix
Comparison Matrix for Boundary Scan Cells.
Comparison matrix
Instruction sets and access modes trade debug speed and attack surface.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Conservative | safe | higher cost | ramp-sensitive |
| Balanced | practical | needs rigor | production |
| Aggressive | fast | escape risk | schedule pressure |
| Architecture | durable | slow | repeated pain |
+------------------+----------------+----------------+----------------+When to choose each approach
Tie approach to product risk and tester constraints
Interview traps
Optimizing one metric only
No regression ownership
Evidence comparison
DFT EVIDENCE MATRIX - Boundary Scan Cells
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report | fault detect trends | silicon root cause | inspect bucket details |
| pattern diff | generation changes | architecture quality | replay suspect patterns |
| timing/power report| test closure margin | diagnosis confidence | correlate fail logs |
| diagnosis summary | likely defect classes | ownership decision | assign action owner |
| signoff checklist | process completeness | correctness of evidence | peer review artifacts |
+-------------------+------------------------+--------------------------+-------------------------+DFT deep dive
Boundary scan and JTAG are board-level contracts, not just RTL features.
Concept diagram
JTAG ACCESS
TAP controller -> instruction register -> boundary/data register -> board test/debugMetric graph
BOARD TEST READINESS
instruction coverage vs pin controllabilityReports and artifacts
TAP compliance report
boundary cell coverage matrix
EXTEST/INTEST results
debug lock policy log
Mini case study
Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.
Debug branches
Verify TAP state transitions
Audit package pin ownership
Check security lifecycle lock behavior
Senior review question
Ask: what evidence proves this DFT decision is safe for production?
Key takeaways
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Common pitfalls
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Principal DFT review addendum
Boundary scan cells wrap IO pins so interconnects can be tested independently from core logic using standard JTAG instructions.
Metric: boundary cell insertion coverage, pin-level controllability, EXTEST pass rate