Fault Models

What this topic teaches

Fault Models turns DFT intent into measurable release confidence. Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When stuck-at / transition / bridge coverage, untestable fault ratio moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - Fault Models

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Fault model stack

fault model ladder
1) stuck-at
2) transition
3) bridge/path-delay/cell-aware

Each rung improves quality and increases runtime/pattern cost.

Process sequence

DFT FLOW - Fault Models

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: stuck-at / transition / bridge coverage, untestable fault ratio

Ownership layers

DFT OWNERSHIP LAYERS - Fault Models

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: stuck-at / transition / bridge coverage, untestable fault ratio.

• Primary artifact: fault coverage report, fault class breakdown, untestable list.

• Owners to bring into review: ATPG owner, DFT architect, quality owner.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - Fault Models

artifact              owner
----------------      -----------------
architecture/report ATPG owner
constraints/setup   DFT architect
physical/test       quality owner

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.