Step-by-step analysis walkthrough

Use when you own Fault Models in a DFT closure review.

1. Open release criteria and failing metric dashboard.

2. Partition failures by pattern family and operating context.

3. Inspect constraints, clocks, masks, and unknown handling.

4. Check architecture assumptions against implementation reality.

5. Review diagnosis evidence for repeatability.

6. Assign owner and propose smallest high-confidence change.

7. Run timing, power, and quality regressions.

8. Capture final signoff or waiver decision.

Artifacts to collect

• fault coverage report, fault class breakdown, untestable list

• pattern tag manifest

• tester program revision

• signoff checklist

• owner tracker

Decision memo template

DFT DECISION MEMO - Fault Models
scenario:
metric:
hypothesis:
fix:
regression:
owners: ATPG owner, DFT architect, quality owner

Reference visuals

Fault model stack

fault model ladder
1) stuck-at
2) transition
3) bridge/path-delay/cell-aware

Each rung improves quality and increases runtime/pattern cost.

DFT deep dive

ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

Concept diagram

ATPG FLOW

fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

Metric graph

COVERAGE GAP

target coverage
  ^
  |      o before closure
  |          o after fixes
  +---------------------> iteration

Reports and artifacts

• fault model coverage

• untestable class report

• constraint legality errors

• pattern signoff memo

Mini case study

Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

Debug branches

• Classify untestable faults

• Diff ATPG constraints each run

• Pair coverage with pattern budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Fault models define what manufacturing defects ATPG targets; model mix drives pattern count, runtime, and outgoing quality.

Metric: stuck-at / transition / bridge coverage, untestable fault ratio